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| DATA SHEET MOS INTEGRATED CIRCUIT PD17068 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY SYNTHESIZER FOR DIGITAL TUNING SYSTEMS The PD17068 is a 4-bit single-chip microcontroller for digital tuning systems. It contains an image display controller (IDC) that supports many types of display, and a PLL synthesizer. The CPU of the PD17068 is capable of 4-bit parallel addition, logical operations, bit tests, setting/resetting of a carry flag, and supports a powerful interrupt function and timer function. The image display controller for on-screen display is user-programmable, allowing a range of displays to be programmed. The peripheral hardware includes a full complement of I/O ports, controlled with powerful I/O instructions, as well as a serial interface, a 6-bit A/D converter, and an 8-bit D/A converter (PWM output). FEATURES * * * * * * * * * * * * * * * * Program memory (ROM) : 24K bytes (12032 x 16 bits) Character ROM (CROM) : 4086 x 24 bits (255 characters) Data memory (RAM) : 1007 x 4 bits Video RAM (VRAM) : 672 x 4 bits (can be used for data memory) Address stack : 12 levels Interrupt stack : 2 levels Instruction execution time : 2 s (when an 8 MHz crystal is used) PLL frequency synthesizer 8-bit serial interface (2 channels: One for two-wire or three-wire mode, compatible with I2C bus, and one for three-wire mode only) D/A converter: 8 bits x 9 lines (PWM output) A/D converter: 6 bits x 8 lines Horizontal synchronizing signal counter Commercial power supply frequency counter Power-failure detection circuit and power-on reset circuit Interrupt input for remote-controller signal (with noise canceler) User-programmable image display controller (IDC) Displayed characters : Up to 192 per screen (more characters can be displayed when the use of the entire screen is specified with a program) Display mode : 16 x 16 dots in 15 lines x 24 columns 14 x 16 dots in 17 lines x 24 columns Character patterns : 255 Character format : 16 x 16 dots or 14 x 16 dots Colors : 15 Character sizes : 16 sizes for height (can be specified per line) 24 sizes for width (can be specified per character) Many I/O ports I/O : 19 ports Input only : 4 ports Output only : 21 ports Operating supply voltage: 5 V 10 % Low power dissipation by use of CMOS technology The information in this document is subject to change without notice. Document No. IC-3525 (O.D. No. IC-8999) Date Published November 1994 P Printed in Japan * * * (c) 1994 PD17068 ORDERING INFORMATION Part number Package 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Quality grade Standard Standard PD17068GF-xxx-3BA PD17068GF-Exx-3BANote Note Product supporting an I2C bus interface. When using the I2C bus interface (including implementation with a program that does not use peripheral hardware), make this point clear to your NEC sales representative when ordering mask options. Remark xxx is a ROM code. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 PD17068 FUNCTION OVERVIEW Item Program memory (ROM) * 24K bytes (12032 x 16 bits) Table reference area: 12032 x 16 bits Character ROM (CROM) Data memory RAM * 4086 x 24 bits (255 characters) * 1007 x 4 bits (including area also used for VRAM) Data buffers: 4 x 4 bits, general-purpose registers: 16 x 4 bits Video RAM (VRAM) System registers Register files General-purpose port registers Instruction execution time Stack levels General-purpose ports * 672 x 4 bits (can be used for data memory (RAM)) * 12 x 4 bits * 12 x 4 bits * 12 x 4 bits * 2 s (when 8 MHz crystal is used) * 12 levels (stack manipulation possible) * I/O Input only : 19 ports : 4 ports Function Output only : 21 ports IDC (Image Display Controller) * Displayed characters : Up to 192 per screen (more characters can be displayed when the use of the entire screen is specified with a program) * Display mode * Character patterns * Character format * Colors * Character sizes : 16 x 16 dots in 15 lines x 24 columns 14 x 16 dots in 17 lines x 24 columns : 255 (user-programmable) : 16 x 16 dots or 14 x 16 dots (2-dot interval can be specified between characters.) : 15 : 16 different heights (can be specified per line) 24 different widths (can be specified per character) PLL frequency synthesizer * Frequency division method : Pulse swallow * Reference frequency : 5, 6.25, 10, 12.5, and 25 kHz * Contains a charge pump for an external low-pass filter * Phase comparator : Unlock can be detected with a program. The delay for the unlock flip-flop is selectable. Serial interface * 2 channels Serial interface 0 (two-wire or three-wire mode, compatible with I2C bus) Serial interface 1 (three-wire mode only) D/A converter A/D converter Interrupts * 8 bits x 9 lines (PWM output with withstand voltage of 12.5 V max.) * 6 bits x 8 lines (successive approximation system with software) * 10 channels (maskable interrupts) External interrupts : 3 channels (INT0, INTNC, and VSYNC/HSYNC) Internal interrupts : 7 channels (timers 0 and 1, serial interfaces 0 and 1, basic timer 2, VRAM pointer, and timer 0 overflow) 3 PD17068 Item Timers Timer 0 Timer 1 Function : 10 s to 204.75 ms (interrupt) : 1 s to 256 ms (interrupt) Basic timer 0 : 1, 5, and 100 ms (carry) Basic timer 1 : 125 s, 1 ms, 5 ms, 100 ms, and external (carry) Basic timer 2 : 125 s, 1 ms, 5 ms, 100 ms, and external (interrupt) Watch timer : Day, hour, minute, and second (count value) Reset * Power-on reset * Reset with the CE pin (by switching the CE pin from low to high) * Power-failure detection function Supply voltage Package 5 V10% 100-pin plastic QFP (14 x 20 mm) Remark Parentheses for timers indicate how to obtain the elapsed time for each timer. Interrupt Carry Count value : Receiving an interrupt : Detecting the state of the carry flip-flop : Reading the count value 4 PD17068 BLOCK DIAGRAM ADC0 ADC1 (P0D0/XTOUT) ADC2 (P0D1/XTIN) ADC3 (P0D2) ADC4 (P0D3) ADC5 (P1C0) | VCO PSC EO OSCIN OSCOUT HSYNC VSYNC RED GREEN BLUE BLANK I (POB2) Hsync counter OSC ALU Watch timer IDC RF PLL RAM 1007 x 4 bits OSC circuit VRAM (672 x 4 bits) System registers D/A converter A/D Converter ADC7 (P1C2) PWM0 (P2C0) | PWM3 (P2C3) PWM4 (P2B0) | PWM7 (P2B3) PWM8 (P2A0) XTIN (P0D1/ADC2) XTOUT (P0D0/ADC1) CKOUT (P1B1) HSCNT (P0B3) Timer 0 P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P1A0-P1A3 P1B0-P1B3 P1C0-P1C3 P1D0-P1D3 P2A0 P2B0-P2B3 P2C0-P2C3 P2D0-P2D3 XIN XOUT VDD CE RLSSTP/PIB2 GND0, GND1 4 4 4 4 4 Instruction decoder Timer 1 ROM 12032 x 16 bits CROM 4086 x 24 bits Basic timer 0 4 Program counter 4 Basic timer 1 TMIN (P1B3) Port 4 4 Stack 12 x 14 bits Basic timer 2 SDA (P0A0) SCL (P0A1) Serial interface 0 SCK0 (P0A2) SO0 (P0A3) SI0 (P0B0) SCK1 (P2D0) Main OSC CPU Peripheral Interrupt Serial interface 1 SO1 (P2D1) SI1 (P2D2) INTNC Reset INT0 4 3 5 PD17068 PIN CONFIGURATION (TOP VIEW) VDD1 VDD0 XIN XOUT INTNC XTOUT/ADC1/P0D0 XTIN/ADC2/P0D1 E0 VC0 GND2 GND1 P1D3 CE PSC NC NC NC NC P1D2 P1D1 P1D0 INT0 NC P1B3/TMIN P1B2/RLSSTP NC P1B1/CKOUT P1B0 NC NC P1A3 P1A2 NC NC NC P1A1 P1A0 NC P2A0/PWM8 NC NC P2D2/SI1 P2D1/SO1 P2D0/SCK1 NC GND0 0SCOUT 0SCIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0D2/ADC3 P0D3/ADC4 P1C0/ADC5 P1C1/ADC6 NC P1C2/ADC7 P1C3 NC ADC0 NC P0C0 NC P0C1 NC P0C2 NC P0C3 NC P2C0/PWM0 NC P2C1/PWM1 NC P2C2/PWM2 NC P2C3/PWM3 NC P2B0/PWM4 P2B1/PWM5 P2B2/PWM6 P2B3/PWM7 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P0B3/HSCNT NC NC P0B2/I P0B1 NC P0B0/SI0 P0A3/SO0 P0A2/SCK0 6 P0A1/SCL P0A0/SDA PD17068GF-xxx-3BA PD17068GF-Exx-3BA RED GREEN NC BLUE BLANK HSYNC NC VSYNC NC PD17068 PINS ADC0 - ADC7 BLANK BLUE CE CKOUT EO GREEN HSCNT : A/D converter input : Blanking signal output : Character signal output : Chip enable : Watch timer adjustment output : Error output : Character signal output : Input for horizontal synchronizing signal counter HSYNC I INT0, INTNC OSCIN, OSCOUT P0A0 - P0A3 P0B0 - P0B3 P0C0 - P0C3 P0D0 - P0D3 P1A0 - P1A3 P1B0 - P1B3 : Horizontal synchronizing signal input : Character signal output : Input for external interrupt request signal : LC oscillation I/O for IDC : Port 0A : Port 0B : Port 0C : Port 0D : Port 1A : Port 1B XIN, XOUT XTIN,XTOUT VCO VDD0, VDD1 VSYNC GND0, GND1, GND2 : Ground P1C0 - P1C3 P1D0 - P1D3 P2A0 P2B0 - P2B3 P2C0 - P2C3 P2D0 - P2D2 PSC RED RLSSTP SCL SCK0, SCK1 SDA SI0, SI1 SO0, SO1 TMIN : Port 1C : Port 1D : Port 2A : Port 2B : Port 2C : Port 2D : Pulse swallow control output : Character signal output : Input for clock stop release signal : Shift clock I/O : Shift clock I/O : Serial data I/O : Serial data input : Serial data output : Event input for basic timer 1 or 2 : Local oscillation input : Main power supply : Vertical synchronizing signal input : Main clock oscillation I/O : Watch timer oscillation I/O PWM0 - PWM8 : Pulse width modulation output 7 PD17068 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................... 1.1 1.2 1.3 1.4 LIST OF PIN FUNCTIONS .............................................................................................................. EQUIVALENT CIRCUIT OF EACH PIN .......................................................................................... HANDLING UNUSED PINS ............................................................................................................ NOTES ON USE OF THE CE AND INTNC PINS ............................................................................ 17 17 21 26 28 2. PROGRAM MEMORY (ROM) .................................................................................................... 2.1 2.2 2.3 OUTLINE OF PROGRAM MEMORY .............................................................................................. PROGRAM MEMORY CONFIGURATION ..................................................................................... PROGRAM COUNTER .................................................................................................................... 2.3.1 2.3.2 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.5.1 2.5.2 Program Counter Configuration .................................................................................. Segment Register (SGR) ............................................................................................... Branch Instructions ........................................................................................................ Subroutines ..................................................................................................................... Table Reference .............................................................................................................. System Call ..................................................................................................................... Program Counter and Program Memory Size ........................................................... Last Address of Each Segment .................................................................................... 29 29 30 31 31 31 31 31 32 32 32 33 33 33 PROGRAM FLOW ........................................................................................................................... NOTES ON USE OF PROGRAM MEMORY .................................................................................. 3. ADDRESS STACK (ASK) ............................................................................................................ 3.1 3.2 3.3 3.4 OUTLINE OF ADDRESS STACK .................................................................................................... ADDRESS STACK REGISTERS (ASR) .......................................................................................... STACK POINTER (SP) .................................................................................................................... 3.3.1 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 Configuration and Function of Stack Pointer ............................................................ Subroutine Call Instruction ("CALL addr" or "CALL @AR") and Return Instruction ("RET" or "RETSK") ..................................................................... Table Reference Instruction ("MOVT DBF, @AR") .................................................... Interrupt Reception and Return Instruction ("RETI") ............................................... Address Stack Manipulation Instructions ("PUSH AR", "POP AR") ...................... System Call Instruction ("SYSCAL entry") and Return Instruction ("RET" or "RETSK") ....................................................................................................... NOTES ON USE OF ADDRESS STACK ........................................................................................ 3.5.1 Nesting Level .................................................................................................................. ADDRESS STACK OPERATION ..................................................................................................... 34 34 34 36 36 37 37 37 37 37 37 37 37 4. DATA MEMORY (RAM) ............................................................................................................. 4.1 4.2 OUTLINE OF DATA MEMORY ...................................................................................................... CONFIGURATION AND FUNCTIONS OF DATA MEMORY ....................................................... 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 System Register (SYSREG) ........................................................................................... Data Buffer (DBF) ........................................................................................................... VRAM (Video RAM) for the IDC ................................................................................... Port Register ................................................................................................................... General-Purpose Data memory .................................................................................... Unmounted Data Memory ............................................................................................ 38 38 39 39 39 39 39 39 39 8 PD17068 4.3 4.4 DATA MEMORY ADDRESSING .................................................................................................... NOTES ON USING DATA MEMORY ............................................................................................ 4.4.1 4.4.2 Power-On Reset .............................................................................................................. Notes on Unmounted Data Memory ........................................................................... 42 42 42 42 5. SYSTEM REGISTER (SYSREG) ................................................................................................. 5.1 5.2 5.3 OUTLINE OF SYSTEM REGISTER ................................................................................................ FORMAT OF SYSTEM REGISTER ................................................................................................. ADDRESS REGISTER (AR) ............................................................................................................. 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.5 5.5.1 5.5.2 5.6 Format of Address Register .......................................................................................... Address Register Functions .......................................................................................... Address Register and Data Buffer ............................................................................... Notes on Using Address Register ............................................................................... Format of Window Register ......................................................................................... Window Register Functions ......................................................................................... Format of Bank Register ............................................................................................... Bank Register Functions ............................................................................................... 43 43 44 45 45 46 46 46 47 47 47 48 48 48 49 49 50 52 52 53 53 54 54 55 56 56 WINDOW REGISTER (WR) ............................................................................................................ BANK REGISTER (BANK) .............................................................................................................. INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP: MEMORY POINTER) .............................................................................................................. 5.6.1 5.6.2 Index Register (IX) ......................................................................................................... Data Memory Row Address Pointer (MP) .................................................................. Format of General-Purpose Register Pointer ............................................................. General-Purpose Register Pointer Functions ............................................................. Notes on Using General-Purpose Register Pointer ................................................... Format of Program Status Word ................................................................................. Program Status Word Functions ................................................................................. Notes on Using Program Status Word ....................................................................... 5.7 GENERAL-PURPOSE REGISTER POINTER (RP) .......................................................................... 5.7.1 5.7.2 5.7.3 5.8 PROGRAM STATUS WORD (PSWORD) ...................................................................................... 5.8.1 5.8.2 5.8.3 5.9 NOTES ON USING SYSTEM REGISTER ...................................................................................... 6. GENERAL-PURPOSE REGISTER (GR) ...................................................................................... 6.1 6.2 6.3 OUTLINE OF GENERAL-PURPOSE REGISTER ............................................................................ GENERAL-PURPOSE REGISTER BODY ....................................................................................... GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS ............... 6.3.1 Addition Instructions (ADD r,m, ADDC r,m) Subtraction Instructions (SUB r,m, SUBC r,m) Logical Operation Instructions (AND r,m, OR r,m, XOR r,m) Direct Transfer Instructions (LD r,m, ST m,r), and Rotate Instruction (RORC r) .......................................................................................... 6.3.2 6.4 6.4.1 6.4.2 Indirect Transfer Instructions (MOV @r,m, MOV m,@r) .......................................... Row Address of General-Purpose Register ................................................................ Operation between General-Purpose Register and Immediate Data ..................... NOTES ON USING GENERAL-PURPOSE REGISTER ................................................................. 57 57 57 58 58 58 59 59 59 9 PD17068 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK ................................................................................ 7.1 7.2 OVERVIEW ...................................................................................................................................... CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ............ 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.4 ALU ................................................................................................................................... Temporary Storage Registers A and B ....................................................................... Program Status Word .................................................................................................... Decimal Conversion Circuit .......................................................................................... Address Controller ......................................................................................................... 60 60 61 61 61 61 61 61 61 65 65 65 ALU OPERATIONS ......................................................................................................................... NOTES ON USING THE ALU ........................................................................................................ 7.4.1 7.4.2 Notes on Using the Program Status Word for Operations ..................................... Notes on Performing Decimal Operations ................................................................. 8. REGISTER FILE (RF) ..................................................................................................................... 8.1 8.2 8.3 8.4 OVERVIEW ...................................................................................................................................... CONFIGURATION AND FUNCTIONS OF THE REGISTER FILE ................................................. 8.2.1 Register File Manipulation Instructions (PEEK WR, rf and POKE rf, WR) .............. CONTROL REGISTERS ................................................................................................................... NOTES ON USING THE REGISTER FILE ..................................................................................... 66 66 67 68 68 79 9. DATA BUFFER (DBF) .................................................................................................................. 9.1 9.2 OVERVIEW ...................................................................................................................................... DATA BUFFER MAIN BODY .......................................................................................................... 9.2.1 9.2.2 9.2.3 9.3 9.4 Configuration of the Data Buffer Main Body ............................................................. Instruction to Reference a Table (MOVT DBF, @AR) ................................................ Instructions for Controlling the Peripheral Hardware (PUT, GET) ......................... 80 80 81 81 82 82 82 86 PERIPHERAL HARDWARE AND DATA BUFFER ......................................................................... NOTES ON USING THE DATA BUFFER ...................................................................................... 10. GENERAL-PURPOSE PORTS .................................................................................................... 10.1 10.2 OVERVIEW ...................................................................................................................................... GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C, P2D) ................................................... 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.4.1 10.4.2 10.4.3 Configurations of the I/O ports ................................................................................... Using the I/O Port .......................................................................................................... Control Registers of the I/O Ports ............................................................................... Using an I/O Port as an Input Port .............................................................................. Using an I/O Port as an Output Port ........................................................................... Notes on Using the I/O Port ......................................................................................... Statuses of the I/O Ports upon Reset ......................................................................... Configuration of the Input Port ................................................................................... Using the Input Port ...................................................................................................... 87 87 89 89 92 93 98 98 98 99 99 99 99 GENERAL-PURPOSE INPUT PORT (P0D) .................................................................................... Notes on Using the Input Port ..................................................................................... 100 Statuses of the Input Port upon Reset ....................................................................... 100 Configurations of the Output Ports ............................................................................. 100 Using the Output Port ................................................................................................... 101 Statuses of the Output Port upon Reset .................................................................... 101 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A, P1D, P2A, P2B, P2C) ................................. 100 10 PD17068 11. INTERRUPT ................................................................................................................................. 102 11.1 11.2 OUTLINE OF THE INTERRUPT BLOCK ........................................................................................ 102 INTERRUPT CONTROL BLOCKS ................................................................................................... 104 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.4 11.5 11.6 Formats and Functions of Interrupt Request Flags (IRQxxx) .................................. 104 Interrupt Enable Flags (IPxxx) ...................................................................................... 110 Vector Address Generator (VAG) ................................................................................ 112 Format and Functions of the Interrupt Stack Register ............................................ 113 Interrupt Stack Operation ............................................................................................. 113 INTERRUPT STACK REGISTER ..................................................................................................... 113 STACK POINTER, ADDRESS STACK REGISTER, AND PROGRAM COUNTER ....................... 114 INTERRUPT ENABLE FLIP-FLOP (INTE) ....................................................................................... 114 ACCEPTING INTERRUPTS ............................................................................................................. 115 11.6.1 11.6.2 Operation for Accepting Interrupts and Priorities .................................................... 115 Timing Charts for Accepting Interrupts ...................................................................... 116 11.7 11.8 11.9 OPERATION AFTER AN INTERRUPT IS ACCEPTED .................................................................. 119 RETURN FROM THE INTERRUPT HANDLING ROUTINE........................................................... 119 EXTERNAL INTERRUPTS (INT0 PIN, INTNC PIN, VSYNC PIN, HSYNC PIN) ................................... 120 11.9.1 11.9.2 11.9.3 11.9.4 11.10.1 11.10.2 11.10.3 11.10.4 11.10.5 11.10.6 11.10.7 Outline of External Interrupts ...................................................................................... 120 Edge Detection Blocks ................................................................................................... 121 Interrupt Control Block ................................................................................................. 122 Input Pin for Remote Control (INTNC) .......................................................................... 123 Timer 0 Interrupt ............................................................................................................ 124 Timer 1 Interrupt ............................................................................................................ 124 Basic Timer 2 Interrupt ................................................................................................. 124 VRAM Pointer Interrupt ................................................................................................ 124 Serial Interface 0 Interrupt ........................................................................................... 124 Serial Interface 1 Interrupt ........................................................................................... 124 Interrupts by Interrupt Group 0 and Interrupt Group Selection Register ............. 125 11.10 INTERNAL INTERRUPTS ............................................................................................................... 123 12. TIMERS ........................................................................................................................................ 126 12.1 12.2 OVERVIEW ...................................................................................................................................... 126 BASIC TIMER 0 ............................................................................................................................... 128 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.4 12.4.1 12.4.2 12.4.3 Overview of Basic Timer 0 ............................................................................................ 128 Clock Selection Block .................................................................................................... 128 Flip-Flop and BTM0CY Flag .......................................................................................... 129 Example of Using Basic Timer 0 .................................................................................. 130 Time Interval Error in Basic Timer 0 ........................................................................... 131 Cautions for Using Basic Timer 0 ................................................................................ 134 Overview of Basic Timer 1 ............................................................................................ 140 Clock Selection Block .................................................................................................... 141 Flip-Flop and BTM1CY Flag .......................................................................................... 142 Time Interval Error in Basic Timer 1 ........................................................................... 142 Overview of Basic Timer 2 ............................................................................................ 143 Clock Selection Block .................................................................................................... 144 Example of Using Basic Timer 2 .................................................................................. 145 BASIC TIMER 1 ............................................................................................................................... 140 BASIC TIMER 2 ............................................................................................................................... 143 11 PD17068 12.4.4 12.4.5 12.5 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.5.6 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 12.7 12.7.1 12.7.2 12.7.3 12.7.4 12.7.5 12.7.6 Time Interval Error in Basic Timer 2 ........................................................................... 145 Cautions for Using Basic Timer 2 ................................................................................ 148 Overview of Timer 0 ...................................................................................................... 150 Clock Selection Block .................................................................................................... 151 Count Block ..................................................................................................................... 152 Example of Using Timer 0 ............................................................................................ 155 Time Interval Error in Timer 0 ...................................................................................... 156 Cautions for Using Timer 0 .......................................................................................... 156 Overview of Timer 1 ...................................................................................................... 157 Clock Selection Block .................................................................................................... 158 Count Block ..................................................................................................................... 159 Time Interval Error in Timer 1 ...................................................................................... 161 Cautions for Using Timer 1 .......................................................................................... 161 Overview of the Clock Timer ........................................................................................ 162 Clock Frequency Divider Block ..................................................................................... 163 Count Block ..................................................................................................................... 165 Reset Control Block ....................................................................................................... 169 32 kHz Oscillator and Oscillation Frequency Adjustment ........................................ 170 Cautions for Using the Clock Timer ............................................................................ 170 TIMER 0 ........................................................................................................................................... 150 TIMER 1 ........................................................................................................................................... 157 CLOCK TIMER ................................................................................................................................. 162 13. A/D CONVERTER ....................................................................................................................... 171 13.1 13.2 13.3 13.4 13.5 13.6 OUTLINE OF A/D CONVERTER .................................................................................................... 171 INPUT SWITCHING BLOCK ........................................................................................................... 172 COMPARE VOLTAGE GENERATION BLOCK AND COMPARE BLOCK .................................... 174 COMPARE TIMING CHART ........................................................................................................... 178 A/D CONVERTER PERFORMANCE .............................................................................................. 178 USING A/D CONVERTER .............................................................................................................. 179 13.6.1 13.6.2 13.7 13.8 Comparison with One Reference Voltage .................................................................. 179 Successive Approximation Based on the Binary Search Method .......................... 180 NOTES ON USING A/D CONVERTER .......................................................................................... 184 STATES UPON RESET ................................................................................................................... 184 13.8.1 13.8.2 13.8.3 Power-On Reset .............................................................................................................. 184 Clock Stop ....................................................................................................................... 184 CE Reset .......................................................................................................................... 184 14. D/A CONVERTER (PWM METHOD) ......................................................................................... 185 14.1 14.2 14.3 14.4 14.5 14.6 14.7 OUTLINE OF D/A CONVERTER .................................................................................................... 185 OUTPUT SWITCHING BLOCK ....................................................................................................... 186 DUTY CYCLE SETTING BLOCK ..................................................................................................... 188 CLOCK GENERATION BLOCK ....................................................................................................... 190 OUTPUT WAVEFORMS OF D/A CONVERTER ........................................................................... 190 NOTES ON USING D/A CONVERTER .......................................................................................... 191 STATES UPON RESET ................................................................................................................... 191 14.7.1 14.7.2 Power-On Reset .............................................................................................................. 191 Clock Stop ....................................................................................................................... 191 12 PD17068 14.7.3 14.7.4 CE Reset .......................................................................................................................... 191 Halt State ........................................................................................................................ 191 15. SERIAL INTERFACE .................................................................................................................... 192 15.1 15.2 GENERAL ......................................................................................................................................... 192 SERIAL INTERFACE 0 ..................................................................................................................... 193 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.2.7 15.2.8 15.2.9 15.2.10 15.2.11 15.2.12 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 General ............................................................................................................................ 193 Clock I/O Control Block and Data I/O Control Block ................................................ 194 Clock Control Block ....................................................................................................... 197 Clock Counter and Start/Stop Detection Block......................................................... 197 Presettable Shift Register 0 .......................................................................................... 199 Wait Control Block and Acknowledge Control Block ............................................... 200 Interrupt Control Block ................................................................................................. 202 I2C Bus Mode ................................................................................................................... 203 Serial I/O Mode .............................................................................................................. 210 Data Write and Read Cautions ..................................................................................... 214 Serial Interface 0 Operation.......................................................................................... 215 State When Serial Interface 0 Is Reset ....................................................................... 218 General ............................................................................................................................ 219 Clock I/O Control Block and Data I/O Control Block ................................................ 219 Clock Counter ................................................................................................................. 220 Presettable Shift Register 1 .......................................................................................... 222 Wait Control Block ......................................................................................................... 222 Serial Interface 1 Operation.......................................................................................... 223 Data Write and Data Read Cautions ........................................................................... 226 Serial Interface 1 Operation.......................................................................................... 227 State When Serial Interface 1 Is Reset ....................................................................... 228 SERIAL INTERFACE 1 ..................................................................................................................... 219 16. IMAGE DISPLAY CONTROLLER (IDC) ..................................................................................... 229 16.1 GENERAL ......................................................................................................................................... 229 16.1.1 16.1.2 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.3 16.3.1 16.3.2 16.3.3 16.4 16.4.1 16.4.2 16.5 16.5.1 16.5.2 Configuration .................................................................................................................. 229 IDC Functions .................................................................................................................. 230 IDC Display Control Block Control Registers ............................................................. 231 Display Format ............................................................................................................... 233 Space between Characters ........................................................................................... 233 Screen Background Color ............................................................................................. 235 Configuration of IDC Start Position Setting Register ............................................... 235 Horizontal Start Position Setting ................................................................................ 236 Vertical Start Position Setting ..................................................................................... 237 Character Pattern Data Configuration ........................................................................ 240 Definition of Character Pattern Data with Assembler .............................................. 242 General ............................................................................................................................ 243 Configuration of VRAM Data ........................................................................................ 244 IDC DISPLAY CONTROL BLOCK ................................................................................................... 231 IDC START POSITION CONTROL BLOCK .................................................................................... 235 CROM (CHARACTER ROM) ........................................................................................................... 239 VRAM (VIDEO RAM) ...................................................................................................................... 243 13 PD17068 16.5.3 16.5.4 16.5.5 16.5.6 16.5.7 16.6 16.6.1 16.6.2 16.6.3 16.7 16.7.1 16.7.2 16.8 16.8.1 Character Pattern Selection Data ................................................................................ 245 Carriage Return Data (C/R) ........................................................................................... 248 Control Data .................................................................................................................... 248 VRAM Data Setting Example ....................................................................................... 253 VRAM Data Setting Cautions ....................................................................................... 253 Configuration of VRAM Pointer ................................................................................... 255 VRAM Pointer Buffer (IDCVP) ....................................................................................... 256 VRAM Pointer Register (IDCVPR) ................................................................................ 257 Functions of IDC Output Pins ....................................................................................... 258 IDC Output Waveforms ................................................................................................. 258 Displaying Data Exceeding VRAM Capacity (Extended Display Mode) ................. 259 VRAM POINTER .............................................................................................................................. 255 IDC OUTPUT PINS (BLANK, RED, GREEN, BLUE, I PINS) ........................................................ 258 SAMPLE PROGRAM ....................................................................................................................... 259 17. HORIZONTAL SYNCHRONIZING SIGNAL COUNTER ............................................................ 262 17.1 17.2 17.3 GENERAL ......................................................................................................................................... 262 GATE INPUT AMPLIFIER ............................................................................................................... 262 GATE CONTROL ............................................................................................................................. 263 17.3.1 17.3.2 17.4 17.5 17.6 HSYNC Counter Gate Mode Selection Flag (HSCGTx) ................................................ 264 HSYNC Counter Gate Open Status Flag (HSCGOSTT) ................................................ 264 HSYNC COUNTER DATA REGISTER (HSC) .................................................................................... 265 SAMPLE PROGRAM ....................................................................................................................... 265 STATE AT RESET ........................................................................................................................... 265 18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 266 18.1 18.2 GENERAL ......................................................................................................................................... 266 PROGRAMMABLE DIVIDER .......................................................................................................... 267 18.2.1 18.2.2 18.3 18.4 Configuration .................................................................................................................. 267 Programmable Divider and PLL Data Register .......................................................... 268 REFERENCE FREQUENCY GENERATOR ..................................................................................... 269 PHASE COMPARATOR ( -DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK ......... 271 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 Configuration of Phase Comparator, Charge Pump and Unlock Detection Block ................................................................................................. 271 Phase Comparator Functions ....................................................................................... 271 Charge Pump .................................................................................................................. 272 Configuration and Functions of Unlock Detection Block ......................................... 273 Organization and Functions of PLL Unlock Flip-Flop Judge Register .................... 273 Organization and Functions of PLL Unlock Flip-Flop Sensibility Selection Register .......................................................................................................... 274 18.5 18.6 18.7 18.8 PLL DISABLED STATE ................................................................................................................... 274 PLL FREQUENCY SYNTHESIZER USE ......................................................................................... 275 SAMPLE PROGRAM ....................................................................................................................... 276 STATE AT RESET ........................................................................................................................... 277 18.8.1 18.8.2 18.8.3 18.8.4 At Power-On Reset ........................................................................................................ 277 At Clock-Stop .................................................................................................................. 277 At CE Reset ..................................................................................................................... 277 During the Halt State .................................................................................................... 277 14 PD17068 19. STANDBY .................................................................................................................................... 278 19.1 19.2 STANDBY FUNCTIONS .................................................................................................................. 278 HALT FUNCTION ............................................................................................................................ 280 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.3 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.4 19.5 19.6 General ............................................................................................................................ 280 Halt State ........................................................................................................................ 280 Halt Release Conditions ................................................................................................ 280 Halt Release by Key Input ............................................................................................. 281 Halt Release by Basic Timer 0 ...................................................................................... 283 Halt Release by Interrupt .............................................................................................. 283 When Multiple Release Conditions Set Simultaneously.......................................... 286 Clock-Stop State ............................................................................................................ 287 Clock-Stop State Release .............................................................................................. 287 Clock-Stop Release by CE Reset .................................................................................. 287 Clock-Stop Release by Power-On Reset ..................................................................... 288 Clock-Stop Release by R1B2/RLSSTP Pin ..................................................................... 289 Cautions When Using Clock-Stop Instruction ........................................................... 291 CLOCK-STOP FUNCTION .............................................................................................................. 287 DEVICE OPERATION AT HALT AND CLOCK-STOP .................................................................... 292 PIN PROCESSING CAUTIONS IN HALT STATE AND CLOCK-STOP STATE ........................... 293 DEVICE OPERATION CONTROL BY CE PIN ................................................................................ 296 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.6.6 19.6.7 Image Display Controller (IDC) Operation Control.................................................... 296 PLL Frequency Synthesizer Operation Control ......................................................... 296 Clock-Stop Instruction Disable/Enable Control ......................................................... 296 Device Reset ................................................................................................................... 296 Signal Input to CE Pin ................................................................................................... 297 Organization and Functions of CE Pin Level Judge Register .................................. 297 Organization and Functions of CE Pin Edge Detection Register ............................ 298 20. Reset ............................................................................................................................................ 299 20.1 20.2 20.3 RESET BLOCK CONFIGURATION ................................................................................................. 299 RESET FUNCTION .......................................................................................................................... 300 CE RESET ......................................................................................................................................... 301 20.3.1 20.3.2 20.3.3 20.4 20.4.1 20.4.2 20.4.3 20.5 20.5.1 20.5.2 20.5.3 20.5.4 20.6 20.6.1 20.6.2 20.6.3 20.6.4 CE Reset When Clock-Stop (STOP s Instruction) Not Used .................................... 301 CE Reset When Clock-Stop (STOP s Instruction) Used ............................................ 302 Cautions at CE Reset ..................................................................................................... 303 Power-On Reset at Normal Operation ........................................................................ 305 Power-On Reset in Clock-Stop State .......................................................................... 305 Power-On Reset When VDD Rises From 0 V ............................................................... 305 When VDD Pin and CE Pin Rise Simultaneously......................................................... 307 When CE Pin Raised in Forced Halt State Caused by Power-On Reset. ................ 307 When CE Pin Raised After Power-On Reset ............................................................... 307 Cautions When VDD Raised ........................................................................................... 309 Power Failure Detection Circuit ................................................................................... 311 Cautions at Power Failure Detection with BTM0CY Flag ........................................ 314 Power Failure Detection by RAM Judgment ............................................................. 316 Cautions at Power Failure Detection by RAM Judgment ........................................ 318 POWER-ON RESET ......................................................................................................................... 304 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET .............................................. 307 POWER FAILURE DETECTION ...................................................................................................... 311 15 PD17068 21. INSTRUCTION SET .................................................................................................................... 319 21.1 21.2 21.3 LIST OF INSTRUCTION SET .......................................................................................................... 319 INSTRUCTIONS .............................................................................................................................. 320 ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS ....................................................... 323 22. RESERVED SYMBOLS ............................................................................................................... 324 22.1 22.2 22.3 22.4 22.5 22.6 22.7 DATA BUFFER (DBF) ...................................................................................................................... 324 SYSTEM REGISTER (SYSREG) ..................................................................................................... 324 VRAM BANK REGISTER ................................................................................................................ 324 PORT REGISTER ............................................................................................................................. 325 REGISTER FILES ............................................................................................................................. 327 PERIPHERAL HARDWARE REGISTER .......................................................................................... 331 OTHERS ........................................................................................................................................... 331 23. ELECTRICAL CHARACTERISTICS ............................................................................................. 332 24. PACKAGE DRAWINGS ............................................................................................................... 335 25. RECOMMENDED SOLDERING CONDITIONS ....................................................................... 336 APPENDIX A. NOTES ON CONNECTING A CRYSTAL ................................................................ 337 APPENDIX B. DEVELOPMENT TOOLS .......................................................................................... 338 16 PD17068 1. PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS (1) Port pins Pin P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 | P0C3 P0D0 P0D1 P0D2 P0D3 P1A0 | P1A3 P1B0 P1B1 P1B2 P1B3 P1C0 | P1C2 P1C3 P1D0 | P1D3 P2A0 P2B0 | P2B3 P2C0 | P2C3 P2D0 P2D1 P2D2 4-bit output port Output CMOS push-pull Outputs undefined data. Outputs undefined data. Outputs undefined data. Outputs undefined data. Input PWM3 PWM4 | PWM7 PWM0 | PWM3 SCK1 SO1 SI1 4-bit I/O port. Input or output mode can be specified in 4-bit units. I/O CMOS push-pull Input 4-bit output port Output N-ch open drain with Outputs intermediate withundefined data. stand voltage and high current CMOS push-pull Input Function 4-bit I/O port. Input or output mode can be specified in bit units. The pins are automatically set to input mode when the power (VDD) is turned on, the clock is stopped, or the device is reset with the CE pin. 4-bit I/O port. Input or output mode can be specified in bit units. The pins are automatically set to input mode when the power (VDD) is turned on, the clock is stopped, or the device is reset with the CE pin. 4-bit output port. Undefined data is output when the power (VDD) is turned on. 4-bit input port I/O I/O Output type N-ch open drain At reset Input Also used as: SDA SCL CMOS push-pull SCK0 SO0 I/O CMOS push-pull Input SI0 - I HSCNT Output CMOS push-pull Outputs undefined data. Input with a pulldown registor - Input - ADC1/XTOUT ADC2/XTIN ADC3 ADC4 - 4-bit I/O port. Input or output mode can be specified in bit units. I/O - CKOUT RLSSTP TMIN ADC5 | ADC7 - - 1-bit output port 4-bit output port Output Output N-ch open drain with intermediate withstand voltage N-ch open drain with intermediate withstand voltage N-ch open drain with intermediate withstand voltage CMOS push-pull 4-bit output port Output 3-bit I/O port. Input or output mode can be specified in bit units. The pins are automatically set to input mode when the power (VDD) is turned on, the clock is stopped, or the device is reset with the CE pin. I/O 17 PD17068 (2) Non-port pins Pin INT0 Function Input pin for an external interrupt request signal. An interrupt request is triggered by the rising or falling edge of the signal input to this pin. Input pin for an interrupt request signal with a noise canceler. When inputting a signal subject to much noise, such as a remotecontroller signal, use this pin to facilitate programming. Whether the rising or falling edge of the input signal is used to trigger an interrupt request can be specified with a program. Event input pin for basic timer 1 or 2 Pins for connecting the crystal (32.768 kHz) for the watch timer Output pin for adjusting the watch timer Shift clock I/O pins I/O Input Output type - At reset Input Also used as: - INTNC Input - Input - TMIN XTIN XTOUT CKOUT SCK0 SCK1 SI0 SI1 SO0 SO1 SCL SDA ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 | ADC7 PWM0 | PWM3 PWM4 | PWM7 PWM8 Input - - - Input - PIB3 P0D1/ADC2 P0D0/ADC1 Output I/O CMOS push-pull CMOS push-pull Input Input P1B1 P0A2 P2D0 Serial data input pins Input - Input P0B0 P2D2 Serial data output pins Output CMOS push-pull Input P0A3 P2D1 Shift clock I/O pin Serial data I/O pin Analog input pins for the A/D converter with 6-bit resolution I/O I/O Input N-ch open drain N-ch open drain - Input Input Input P0A1 P0A0 - P0D0/XTOUT P0D1/XTIN P0D2 P0D3 Analog input pins for the A/D converter with 6-bit resolution Output pins for the D/A converter with 8-bit resolution Input - Input P1C0 | P1C2 P2C0 | P2C3 P2B0 | P2B3 P2A0 Output N-ch open drain Low-level output with intermediate or high impedwithstand voltage ance 18 PD17068 Pin EO Function Output pin for the charge pump of the PLL frequency synthesizer. When the divided local oscillation (VCO) frequency is higher than the reference frequency, the output of this pin goes to high level. When the divided frequency is lower than the reference frequency, the output of this pin goes to low level. When the frequencies are the same, this pin enters floating status. Output pin for pulse swallow control. This pin is used to output a signal to change the frequency division ratio to the PB595 dedicated prescaler. Local oscillation input pin. The local oscillation (VCO) output from the tuner is frequency-divided by the PB595 dedicated prescaler and input to this pin (the PB595 is a twomodulus prescaler for up to 1 GHz). Input pin for horizontal synchronizing signal counter. Output pin for the blanking signal for cutting the video signal. The signal is high active. Output pin for the R signal for character data received from the IDC. The signal is high active. Output pin for the G signal for character data from the IDC. The signal is high active. Output pin for the B signal for character data from the IDC. The signal is high active. Output pin for the I signal for character data from the IDC. Input pin for the horizontal synchronizing signal for the IDC. Used to input the active-low horizontal synchronizing signal. Input pin for the vertical synchronizing signal for the IDC. Used to input the active-low vertical synchronizing signal. Pins for connecting the LC oscillation circuit for the IDC. Used to connect a 10 MHz LC oscillation circuit. I/O Output Output type CMOS tristate At reset High impedance Also used as: - PSC Output CMOS push-pull Output - VCO Input - Internally pulleddown - HSCNT BLANK Input Output - CMOS push-pull Input Low-level output P0B3 - RED Output CMOS push-pull Low-level output - GREEN Output CMOS push-pull Low-level output - BLUE Output CMOS push-pull Low-level output - I HSYNC Output Input CMOS push-pull - Input Input P0B2 - VSYNC Input - Input - OSCIN OSCOUT - - - - 19 PD17068 Pin CE Function Input pin for the device operation selection signal and reset signal. (1) Device operation selection signal When the device operation selection signal at the CE pin is high, the PLL frequency synthesizer and IDC are enabled. When the signal is low, the PLL frequency synthesizer and IDC are disabled. (2) Reset signal When the reset signal at the CE pin is changed from low to high, the device is reset in synchronization with the internal carry flip-flop for basic interval timer 0. Input pin for the clock stop release signal Pins for connecting a crystal (8 kHz) for the main clock Main power supply pins. Supply 5 V10% when operating the entire device. Supply 4.0 to 5.5 V when the IDC is not being used. The minimum supply voltage is 2.5 V in the clock-stop state. A power-on reset circuit is provided. When the supply voltage increases from 0 to 4.0 V, the system is reset and the program restarts at address 0. The voltage must increase from 0 to 4.0 V within 500 ms to enable correct operation of the power-on reset circuit. Ground pins I/O Input Output type - At reset Input Also used as: _ RLSSTP XIN XOUT VDD0 Input - - - Input - P1B2 - - - - - VDD1 GND0 | GND2 NC - - - - No connection - - - - 20 PD17068 1.2 EQUIVALENT CIRCUIT OF EACH PIN (1) P0A (P0A3/SO0, P0A2/SCK0) P0B (P0B2/I, P0B1, P0B0/SI0) P1B (P1B2/RLSSTP, P1B1/CKOUT, P1B0) P1C (P1C3, P1C2/ADC7, P1C1/ADC6, P1C0/ADC5) A/D converter (only for P1C/ADC) VDD (I/O) RES signal (except for P1C) A/D converter channel select signal (only for P1C) VDD (2) P2D (P2D2/SI1, P2D1/SO1, P2D0/SCK1) : (I/O) VDD RES signal VDD 21 PD17068 (3) P0A (P0A1/SCL, P0A0/SDA) : (I/O) VDD RES signal (4) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1, P1D0) RED, GREEN, BLUE, BLANK PSC VDD (Output) (5) P1A (P1A3, P1A2, P1A1, P1A0) P2A (P2A0/PWM8) P2B (P2B3/PWM7, P2B2/PWM6, P2B1/PWM5, P2B0/PWM4) P2C (P2C3/PWM3, P2C2/PWM2, P2C1/PWM1, P2C0/PWM0) (Output) (6) P0D (P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN, P0D0/ADC1/XTOUT) : (Input) VDD High on-state resistance 22 PD17068 (7) ADC0 : (Input) VDD (8) P0B3/HSCNT : (I/O) VDD Read instruction VDD Port Horizontal synchronizing signal counter 23 PD17068 (9) P1B3/TMIN : (I/O) VDD Read instruction Port VDD VDD Timer counter VDD (10) HSYNC, VSYNC, CE, INT0, INTNC : (Schmitt-triggered input) VDD 24 PD17068 (11) XIN, OSCIN XOUT, OSCOUT : (Input) : High on-state resistance VDD VDD XIN, OSCIN XOUT, OSCOUT (12) EO : (Output) VDD (13) VCO : (Input) VDD VDD (Input) 25 PD17068 1.3 HANDLING UNUSED PINS Connect unused pins as follows: Table 1-1 Handling Unused Pins (1/2) Pin P0A0/SDA P0A1/SCL P0A2/SCK0 P0A3/SO0 P0B0/SI0 P0B1 P0B2/I P0B3/HSCNT P0C0 | P0C3 P0D0/ADC1/XTOUT P0D1/ADC2/XTIN P0D2/ADC3 P0D3/ADC4 P1A0 | P1A3 P1B0 P1B1/CKOUT P1B2/RLSSTP P1B3/TMIN P1C0/ADC5 | P1C2/ADC7 P1C3 P1D0 | P1D3 P2A0/PWM8 P2B0/PWM4 | P2B3/PWM7 P2C0/PWM0 | P2C3/PWM3 P2D0/SCK1 P2D1/SO1 P2D2/SI1 I/O Output Output I/O I/O I/O Recommended connection when not used Input: Connect to VDD or VSS. Output: Output a low and leave open. Input: Connect to VDD or VSS. Output: Leave open. Leave open. Input with a pull-down resistor. Leave open or connect to VSS. N-ch open-drain output Output a low and leave open. I/O Input: Connect to VDD or VSS. Output: Leave open. Leave open. N-ch open-drain output Output a low and leave open. Input: Connect to VDD or VSS. Output: Leave open. 26 PD17068 Table 1-1 Handling Unused Pins (2/2) Pin EO PSC VCO BLANK RED GREEN BLUE HSYNC VSYNC OSCIN OSCOUT ADC0 INT0 INTNC Input Output I/O Recommended connection when not used Leave open. Input with a pull-down resistor Output Leave open or connect to VSS. Leave open. Connect to VDD or VSS. Input with a pull-down resistor Output Input Leave open or connect to VSS. Leave open. Connect to VDD or VSS. 27 PD17068 1.4 NOTES ON USE OF THE CE AND INTNC PINS The CE and INTNC pins support a test mode for selecting the function for testing the internal operation of the PD17068 (IC test), in addition to the functions described in Section 1.1. Applying a voltage exceeding VDD to the CE or INTNC pin causes the PD17068 to enter test mode. If noise exceeding VDD is encountered during normal operation, the device will be switched to test mode. For example, if the wiring from the CE or INTNC pin is too long, noise may be induced in the wiring, thus resulting in this mode switching. When installing wiring, route the wiring such that noise is suppressed as much as possible. If, however, noise arises, use an external part to suppress it as shown below. q Connect a diode with low VF between the pin and VDD. VDD VDD q Connect a capacitor between the pin and VDD. VDD VDD Diode with low VF CE, INTNC CE, INTNC 28 PD17068 2. PROGRAM MEMORY (ROM) 2.1 OUTLINE OF PROGRAM MEMORY Fig. 2-1 outlines program memory. As shown, program memory is addressed with a program counter. Program memory has the following functions: (1) Storing programs (2) Storing constant data Fig. 2-1 Outline of Program Memory Program counter Addressing Program memory Instruction Constant data 29 PD17068 2.2 PROGRAM MEMORY CONFIGURATION Fig. 2-2 shows the configuration of program memory. As shown, program memory consists of 24K bytes (12032 x 16 bits). Program memory therefore has addresses 0000H to 2FFFH. Program memory addresses 3000H to 4FDFH are assigned to the CROM (character ROM) area. This area cannot be used as an ordinary program area. All PD17068 instructions are 16-bit one-word instructions. Each instruction can be stored at a single address of program memory. Constant data stored in program memory is read into the data buffer by executing a table reference instruction. Fig. 2-2 Program Memory Configuration 16 bits 0000H Page 0 07FFH 0800H Page 1 Segment 0 1000H Page 2 17FFH 1800H 1EFFH 1F00H 1FFFH 2000H 27FFH 2800H Page 1 Segment 1 2FFFH (system segment) 3000H Page 3 Undefined Page 0 2000H 20FFH 2100H 21FFH 2200H 22FFH 2300H 25FFH 2600H 26FFH 2700H 27FFH 3FFFH 4000H CROM area Note (cannot be used as program area) Block 0 Block 1 Block 2 Block 6 Block 7 Segment 2 4FDFH Note Addresses in the CROM area are specified with VRAM. Addresses that can be specified with VRAM are 3000H to 3FEFH. An address in the CROM area, however, has 32 bits because CROM data is represented in 24-bit units. Therefore, the CROM addresses which are actually used (actual addresses) are 3000H to 4FDFH (see Chapter 16). 30 PD17068 2.3 2.3.1 PROGRAM COUNTER Program Counter Configuration Fig. 2-3 shows the configuration of the program counter. As shown, the program counter consists of a 13-bit binary counter and 1-bit segment register (SGR). Bits 11 and 12 indicate a page. The program counter is used to specify an address in program memory. Fig. 2-3 Program Counter Configuration SGR PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC PC4 PC3 PC2 PC1 PC0 Page 2.3.2 Segment Register (SGR) The segment register specifies a segment of program memory. Table 2-1 lists the correspondence between segment register values and program memory segments. The segment register is set when a SYSCAL entry instruction is executed. Table 2-1 Correspondence between Segment Register Values and Program Memory Segments Segment register value 0 1 Program memory segment Segment 0 Segment 1 2.4 PROGRAM FLOW The execution flow of a program is controlled with the program counter, which specifies an address in program memory. This section describes the operation of several types of instructions. Fig. 2-4 shows the value set in the program counter when each instruction is executed. Table 2-2 lists the vector addresses when interrupts are received. 2.4.1 Branch Instructions (1) Direct branch ("BR addr") A direct branch instruction can branch only within the same segment of program memory. (2) Indirect branch ("BR @AR") An indirect branch instruction can branch to all addresses of program memory, 0000H to 2FFFH. See also Section 5.3. 31 PD17068 2.4.2 Subroutines (1) Direct subroutine call ("CALL addr") A direct subroutine call instruction can call a subroutine starting at an address in page 0 in program memory. (2) Indirect subroutine call ("CALL @AR") An indirect subroutine call instruction can call a subroutine starting at any address in program memory, 0000H to 2FFFH. See also Section 5.3. 2.4.3 Table Reference A table reference instruction ("MOVT DBF, @AR") can reference all addresses in program memory, 0000H to 2FFFH. See also Sections 5.3 and 9.2.2. 2.4.4 System Call A system call instruction (SYSCAL entry) can call a subroutine starting at any of the first 16 addresses of a block (0 to 7) in page 0 of segment 1. Fig. 2-4 Program Counter Value for Each Instruction Program Counter Instruction Page 0 Page 1 BR addr Page 2 Page 3 CALL addr Hold Value of program counter (PC) SGR b12 b11 b10 b9 0 0 1 1 Hold 0 0 1 0 1 0 Instruction operand (addr) Instruction operand (addr) b8 b7 b6 b5 b4 b3 b2 b1 b0 SYSCAL entry BR @AR CALL @AR MOVT DBF, @AR RET RETSK RETI 1 0 0 entryH 0 0 0 0 entryL Contents of address register Return address: Contents of address stack register (ASR) specified with stack pointer (SP) When an interrupt is received 0 Vector address for the interrupt At power-on reset or CE reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remark entryH : Three high-order bits of entry entryL : Four low-order bits of entry 32 PD17068 Table 2-2 Interrupt Vector Addresses Priority 1 2 3 4 5 6 7 8 9 10 Internal/external External External Internal Internal Internal Internal External Internal Internal Internal Interrupt source INTNC pin INT0 pin Timer 0 Timer 1 Basic timer 2 VRAM pointer Interrupt group 1Note 1 Vector address 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H Serial interface 0 Serial interface 1 Interrupt group 0Note 2 Notes 1. Interrupt group 1 : VSYNC or HSYNC pin 2. Interrupt group 0 : Timer 0 overflow 2.5 2.5.1 NOTES ON USE OF PROGRAM MEMORY Program Counter and Program Memory Size The program counter can specify addresses 0000H to 3FFFH, while the valid program memory addresses are 0000H to 1EFFH and 2000H to 2FFFH. Therefore, do not use an instruction specifying addresses 1F00H to 1FFFH or 3000H to 3FFFH. Program memory addresses 1F00H to 1FFFH contain undefined values. Addresses 3000H to 3FFFH constitute the CROM area, which cannot be specified with the program counter. 2.5.2 Last Address of Each Segment The segment register is not connected the binary counter. The last address of segment 0, 1FFFH, is followed by address 0000H of the same segment. Use instructions such as indirect branch, indirect subroutine call, and system call to specify another segment. 33 PD17068 3. ADDRESS STACK (ASK) 3.1 OUTLINE OF ADDRESS STACK Fig. 3-1 outlines the address stack. The address stack consists of the stack pointer and address stack registers. The stack pointer is used to specify one of the address stack registers. The address stack is used to store the return address when a subroutine call instruction is executed or an interrupt is received. The address stack is also used when a table reference instruction is executed. Fig. 3-1 Outline of Address Stack Stack pointer Addressing Address stack registers Return address 3.2 ADDRESS STACK REGISTERS (ASR) Fig. 3-2 shows the configuration of the address stack registers. There are 13 address stack registers, ASR0 to ASR12, each consisting of 14 bits. ASR12, however, cannot be used, the twelve 14-bit registers (ASR0 to ASR11) actually being used. The most significant bit of each address stack register is the segment register stack (SGRSK), the other 13 bits being used as the program counter stack (PCSK). The address stack is used to store the return address when a subroutine call or table reference instruction is executed or an interrupt is received. 34 PD17068 Fig. 3-2 Configuration of Address Stack Registers Stack pointer (SP) Bits b3 b2 b1 b0 Address Address stack registers (ASR) Bits b13 0H b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SP3 SP2 SP1 SP0 ASR0 1H ASR1 2H ASR2 3H ASR3 4H ASR4 5H ASR5 6H ASR6 7H ASR7 8H ASR8 9H ASR9 AH ASR10 BH ASR11 CH ASR12 (undefined) Cannot be used. 35 PD17068 3.3 3.3.1 STACK POINTER (SP) Configuration and Function of Stack Pointer Fig. 3-3 shows the configuration and function of the stack pointer. The stack pointer is a 4-bit binary counter, used for specifying an address stack register. The value of the stack pointer can be directly read or written with a register manipulation instruction. Fig. 3-3 Configuration and Function of Stack Pointer Flag symbol Name b3 ( S P 3 b2 ( S P 2 b1 ( S P 1 b0 ( S P 0 Address Read/write Stack pointer (SP) 01H R/W Specifies an address stack register (ASR). 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 ASR8 ASR9 ASR10 ASR11 ASR12 Upon reset Power-on Clock stop CE 1 1 1 1 1 1 0 0 0 0 0 0 36 PD17068 3.4 ADDRESS STACK OPERATION 3.4.1 Subroutine Call Instruction ("CALL addr" or "CALL @AR") and Return Instruction ("RET" or "RETSK") When a subroutine call instruction is executed, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. When a return instruction is executed, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.2 Table Reference Instruction ("MOVT DBF, @AR") When a table reference instruction is executed, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. Next, the contents of the program memory address specified with the address register are read into the data buffer. Finally, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.3 Interrupt Reception and Return Instruction ("RETI") When an interrupt is received, the value of the stack pointer is decremented by one, after which the return address is stored in the address stack register specified with the stack pointer. When a return instruction is executed, the contents (return address) of the address stack register specified with the stack pointer are read back into the program counter, after which the value of the stack pointer is incremented by one. 3.4.4 Address Stack Manipulation Instructions ("PUSH AR", "POP AR") When a PUSH instruction is executed, the value of the stack pointer is decremented by one, after which the contents of the address register are transferred to the address stack register specified with the stack pointer. When a POP instruction is executed, the contents of the address stack register specified with the stack pointer are transferred to the address register, after which the value of the stack pointer is incremented by one. 3.4.5 System Call Instruction ("SYSCAL entry") and Return Instruction ("RET" or "RETSK") When a "SYSCAL entry" instruction is executed, the value of the stack pointer is decremented by one, after which the return address and the value of the segment register are stored in the address stack register specified with the stack pointer. When a return instruction is executed, the contents of the address stack register specified with the stack pointer are restored into the program counter and segment register, after which the value of the stack pointer is incremented by one. 3.5 3.5.1 NOTES ON USE OF ADDRESS STACK Nesting Level When the stack pointer contains 0CH, it specifies address stack register ASR12, whose value is undefined. If the user attempts to use subroutine calls or interrupts that exceed 12 levels, without stack manipulation, the program will resume from an undefined address. Therefore, do not attempt such an operation. 37 PD17068 4. DATA MEMORY (RAM) 4.1 OUTLINE OF DATA MEMORY Fig. 4-1 outlines the data memory. As shown in Fig. 4-1, the data memory consists of a general-purpose data memory, system registers, data buffer, and port registers. The data memory is used to store data, transfer data to and from peripheral hardware, set display data, transfer data to and from ports, and control the CPU. Fig. 4-1 Outline of Data Memory Peripheral hardware Data transfer Column address 7 8 9 0 0 1 2 3 4 5 6 A B C D E F Data buffer 1 2 Row address 3 Data memory 4 5 6 7 Port register Port register Port register System register Data transfer Port BANK 0 BANK 1 BANK 2 Port register 38 PD17068 4.2 CONFIGURATION AND FUNCTIONS OF DATA MEMORY Fig. 4-2 shows the configuration of the data memory. As shown in Fig. 4-2, the data memory is divided into banks. Each bank consists of 128 nibbles made up of row addresses 0H to 7H by column addresses 0H to FH. The data memory is divided into the functional blocks described in Sections 4.2.1 through 4.2.6. By using data memory manipulation instructions, 4-bit operations, comparison, decision, and transfer operation can be performed for the data memory. Table 4-1 indicates the data memory manipulation instructions. 4.2.1 System Register (SYSREG) A system register is allocated at addresses 74H-7FH. A system register is allocated, independently of the banks; each bank contains the same system register at addresses 74H-7FH. See Chapter 5 for details. 4.2.2 Data Buffer (DBF) A data buffer is allocated at addresses 0CH-0FH of BANK0. See Chapter 9 for details. 4.2.3 VRAM (Video RAM) for the IDC Addresses 00H-3FH of BANK2 of the data memory can also be used as a VRAM for the IDC. Fig. 4-3 shows the configuration of the VRAM. The VRAM consists of VRAMBANK0-VRAMBANKD, that is, 672 x 16 bits. A VRAMBANK can be specified using the VRAM select register at addresses 73H of BANK2. This area is used when the VRAMSEL flag (RF: address 33H, bit 3) is set to 1. When this area is not used as the VRAM, this area can be used as an ordinary RAM. See Chapter 16 for details. 4.2.4 Port Register A port register is allocated at addresses 70H-73H of BANK0 and BANK1, and at addresses 6FH and 70H72H of BANK2. See Chapter 10 for details. 4.2.5 General-Purpose Data memory The general-purpose data memory consists of the data memory other than the system registers and port registers. The general-purpose data memory is made up of 335 nibbles; 112 nibbles of each of BANK0 and BANK1, and 111 nibbles of BANK2. 4.2.6 Unmounted Data Memory The data memory at addresses 30H-3FH of BANK2 and some portion of the port registers are not allocated for any purpose. For details of the unmounted data memory area, see Section 4.4.2 and Chapter 10. 39 PD17068 Fig. 4-2 Configuration of Data Memory Column address 6789A 0 0 1 Row address 3 4 5 6 7 1 2 3 4 5 B C D E F Data memory BANK0 BANK1 BANK2 System register 0 0 1 Row address 2 3 4 5 6 7 1 2 3 4 5 Column address 6789A B CD E F Data buffer (DBF) Example General-purpose register Address 1AH of BANK0 b3 b2 b1 b0 BANK 0 Port register System register (SYSREG) 0 1 Row address 2 3 4 5 6 7 Port register System register (SYSREG) The same system register is allocated. BANK 1 0 1 Row address 2 3 4 5 6 VRAM area (VRAM when VRAMSEL=1; ordinary RAM when VRAMSEL=0) These addresses are not allocated for any purpose. BANK 1 Port register System register (SYSREG) Specifies a VRAM bank. 7 Port register 40 PD17068 Fig. 4-3 Configuration of VRAM Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F VRAMBANK0-D 0 1 2 Row address 3 4 5 6 7 BANK 2 Fixed at 0 System register Specifies a VRAM bank. Table 4-1 List of Data Memory Manipulation Instructions Function Operation Addition Instruction ADD ADDC SUB SUBC AND OR XOR SKE SKGE SKLT SKNE MOV LD ST SKT SKF Subtraction Logical Comparison Transfer Decision 41 PD17068 4.3 DATA MEMORY ADDRESSING Fig. 4-4 shows how a data memory address is specified. A data memory address is specified with a bank, row address, and column address. A row address and column address are directly specified with a data memory manipulation instruction. A bank is specified with a bank register. See Chapter 5 for details of a bank register. Fig. 4-4 Data Memory Addressing Bank b3 b2 b1 b0 Row address b2 b1 b0 Column address b3 b2 b1 b0 Data memory address Bank register Instruction operand 4.4 4.4.1 NOTES ON USING DATA MEMORY Power-On Reset Upon power-on reset, the contents of the general-purpose data memory are undefined. Initialize the general-purpose data memory as required. 4.4.2 Notes on Unmounted Data Memory If a data memory manipulation instruction is executed for an address in the unmounted data memory, the operations below are performed. (1) Device operation When a read instruction is executed, 0 is read. When a write instruction is executed, no change is made. (2) Assembler (AS17K) operation Normal assembly operation is performed. No error occurs. (3) Emulator (IE-17K) operation When a read instruction is executed, 0 is read. When a write instruction is executed, no change is made. No error occurs. 42 PD17068 5. SYSTEM REGISTER (SYSREG) 5.1 OUTLINE OF SYSTEM REGISTER Fig. 5-1 shows where the system registers are located in the data memory, and also outlines the system register. As shown in Fig. 5-1, a system register is allocated, independently of the banks; each bank contains the same system register at data memory addresses 74H-7FH. The system registers are allocated in the data memory, so that the system registers can be manipulated using any manipulation instructions. A system register consists of seven types of registers for different functions. Fig. 5-1 Location on Data Memory and Outline of System Registers Column address 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 A B C D E F Data memory Row address BANK 0 BANK 1 BANK 2 System register Address 74H 75H 76H 77H 78H 79H Register System register (AR) Window register (WR) Bank register (BANK) Outline Program memory address control Data transfer to and from register files Data memory bank specification Address 7AH 7BH Index register (IX) 7CH 7DH 7EH 7FH Register Data memory row address pointer (MP) General-purpose register pointer (RP) Program status word (PSWORD) Outline Data memory address modification General-purpose register addressing Operation control 43 PD17068 5.2 FORMAT OF SYSTEM REGISTER Fig. 5-2 shows the format of the system register. Fig. 5-2 Format of System Register Address 74H 75H 76H System register 77H 78H 79H Register Address register (AR) Window register (WR) Bank register (BANK) Symbol Bit b3 AR3 b2 b1 b0 b3 AR2 b2 b1 b0 b3 AR1 b2 b1 b0 b3 AR0 b2 b1 b0 b3 WR b2 b1 b0 b3 BANK b2 b1 b0 Data 0 0 0 0 Address 7AH 7BH 7CH 7DH System register 7EH 7FH Index register (IX) Register Data memory row address pointer (MP) IXH Symbol MPH Bit b3 b2 b1 b0 b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 IXM IXL RPH RPL PSW General-purpose register pointer (RP) Program status word (PSWORD) Data M P E 0 0 (IX) 0 0 (RP) B C D C M P C Y Z I X E (MP) 44 PD17068 5.3 5.3.1 ADDRESS REGISTER (AR) Format of Address Register Fig. 5-3 shows the format of the address register. As shown in Fig. 5-3, the address register consists of the 16 bits of 74H-77H (AR3-AR0) of a system register. However, the higher 2 bits are always set to 0, so that the address register actually operates as a 14-bit register. Fig. 5-3 Format of Address Register Address Register Symbol Bit b3 74H 75H 76H 77H Address register (AR) AR3 b2 b1 b0 b3 AR2 b2 b1 b0 b3 AR1 b2 b1 b0 b3 AR0 b2 b1 b0 M S B L S B Data 0 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 Remark Power-on CE : At power-on reset : At CE reset Clock stop : At clock stop instruction execution 45 PD17068 5.3.2 Address Register Functions The address register is used to specify program memory addresses for execution of a table reference instruction (MOVT DBF, @AR), stack manipulation instructions (PUSH AR and POP AR), indirect branch instruction (BR @AR), and indirect subroutine call instruction (CALL @AR). For the address register, a dedicated instruction (INC AR) is available which can increment the address register by 1 at a time. The operation performed when each instruction is executed is described (1) through (5) below. (1) Table reference instruction (MOVT DBF, @AR) The instruction loads the constant data (16 bits) held at the program memory address specified in the address register into the data buffer. Constant data stored at addresses 0000H-2FFFH can be specified using the address register. (2) Stack manipulation instructions (PUSH AR, POP AR) When the PUSH AR instruction is executed, the stack pointer is decremented by 1, then the contents of the address register (AR) are stored in the address stack register pointed to by the decremented stack pointer. When the POP AR is executed, the contents of the address stack register pointed to by the stack pointer are transferred to the address register, then the stack pointer is incremented by 1. (3) Indirect branch instruction (BR @AR) The instruction causes a branch to the program memory address specified by the address register. A branch address from 0000H to 2FFFH can be specified using the address register. (4) Indirect subroutine call instruction (CALL @AR) The subroutine at the program memory address specified by the address register can be called. A subroutine start address from 0000H to 2FFFH can be specified by the address register. (5) Address register increment instruction (INC AR) The instruction increments the address register by 1. The address register consists of 14 bits. When the INC AR instruction is executed, however, the address register operates on a 13-bit basis. This means that the address specified after 1FFFH is not 2000H but 0000H. To increment the address register to 2000H, segment register switching is required. Note, however, that the address specified after 3FFFH is not 2000H but 0000H; in this case, segment register switching is not required. 5.3.3 Address Register and Data Buffer The address register allows data transfer through the data buffer as part of peripheral hardware. See Chapter 9 for details. 5.3.4 Notes on Using Address Register The address register consists of 14 bits, so that it can specify up to 3FFFH. However, the program memory area consists of addresses 0000H-1EFFH and addresses 2000H-2FFFH. Accordingly, a value from 0000H to 1EFFH or from 2000H to 2FFFH must be specified in the address register. 46 PD17068 5.4 5.4.1 WINDOW REGISTER (WR) Format of Window Register Fig. 5-4 shows the format of the window register. As shown in Fig. 5-4, the window register consists of the 4 bits of 78H of a system register. Fig. 5-4 Format of Window Register Address Register Symbol Bit b3 b2 78H Window register (WR) WR b1 b0 M S B L S B Data Upon reset Power-on Clock stop Undefined The previous state is held. CE 5.4.2 Window Register Functions The window register is used to transfer data to and from a register file (RF) described later. For data transfer to and from a register file, the dedicated instructions PEEK WR, rf and POKE rf, WR are used (rf: register file address). The operation performed when each instruction is executed is described in (1) and (2) below. See also Chapter 8. (1) PEEK WR, rf instruction The instruction transfers the contents of the register file addressed by rf to the window register. (2) POKE rf, WR instruction The instruction transfers the contents of the window register to the register file addressed by rf. 47 PD17068 5.5 5.5.1 BANK REGISTER (BANK) Format of Bank Register Fig. 5-5 shows the format of the bank register. As shown in Fig. 5-5, the bank register consists of the 4 bits of 79H (BANK) of a system register. However, the higher 2 bits are always set to 0, so that the bank register actually operates as a 2-bit register. Fig. 5-5 Format of Bank Register Address Register Symbol Bit b3 b2 79H Bank register (BANK) BANK b1 b0 M S B L S B Data 0 0 Upon reset Power-on Clock stop CE 0 0 0 5.5.2 Bank Register Functions The bank register specifies a data memory bank. Table 5-1 indicates the bank register values and specified data memory banks. A bank register is contained in each system register, so that it can be rewritten regardless of the bank currently specified. This means that bank register manipulation is independent of the state of the currently specified bank. Table 5-1 Data Memory Bank Specification Bank register (BANK) b3 0 0 0 0 b2 0 0 0 0 b1 0 0 1 1 b0 0 1 0 1 Data memory bank BANK0 BANK1 BANK2 Not to be set 48 PD17068 5.6 5.6.1 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP: MEMORY POINTER) Index Register (IX) (1) Format of Index Register Fig. 5-6 shows the format of the index register. The index register consists of 11 bits: the lower 3 bits (IXH) of 7AH of the system register, 7BH (IXM), and 7CH (IXL). The lower 2 bits (bits 2 and 1 of 7AH) are always set to 0. In operation to access the VRAM, however, only the higher 1 bit (bit 2 of 7AH) is always set to 0. For the method of VRAM access, see Section 16.5.7. Fig. 5-6 Format of Index Register Address 7AH 7BH Index register (IX) 7CH 7EH 7FH Program status word (PSWORD) Register Memory pointer (MP) IXH Symbol MPH Bit b3 b2 b1 b0 b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 IXM IXL PSW b0 b3 b2 b1 b0 I X E Data memory access M Fixed Fixed at at P 0 0 E BANK M P E Fixed at 0 VRAMBANK IX Row address 0 0 0 Column address 0 0 0 IX Row address Column address VRAM access I X E Upon reset Power-on Clock stop CE 0 0 0 0 0 0 (2) Index register functions The index register is used to modify data memory addresses when a data memory manipulation instruction is executed. That is, the data memory bank, row address, and column address specified by a data memory manipulation instruction are ORed with the contents of the index register, and the instruction is executed for the data memory location specified by the result of OR operation. Note, however, that address modification is enabled only when the IXE flag (bit 0 of 7FH of the system register) is set to 1. A dedicated instruction (INC IX) for incrementing the index register allows easy access to a data memory location. Address modification using the index register can be performed with all data memory manipulation instructions. With the instructions listed below, address modification using the index register is impossible. 49 PD17068 INC INC MOVT PUSH POP PEEK POKE GET PUT BR BR AR IX DBF, @AR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR RORC r CALL addr CALL @AR RET RETSK RETI EI DI STOP s HALT h NOP For details of address modification, see Chapter 7. 5.6.2 Data Memory Row Address Pointer (MP) (1) Format of data memory row pointer Fig. 5-7 shows the format of the data memory row address pointer (referred to as the memory pointer). The memory pointer consists of 7 bits: the lower 3 bits (MPH) of 7AH of the system register, and 7BH (MPL) of the system register. The higher 2 bits (bits 2 and 1 of 7AH) are always set to 0. In operation to access the VRAM, however, only the higher 1 bit (bit 2 of 7AH) is always set to 0. For the method of VRAM access, see Section 16.5.7. (2) Memory pointer functions When the general-purpose register indirect transfer instructions (MOV @r,m and MOV m,@r) are executed, the memory pointer is used to modify the indirect transfer destination address @r. That is, the bank and row address of the indirect transfer destination specified by an instruction is replaced with the contents of the memory pointer. Note, however, that address modification is enabled only when the MPE flag (bit 3 of 7AH of the system register) is set to 1. Address modification using the memory pointer can be performed only with the general-purpose register indirect transfer instructions. 50 PD17068 Fig. 5-7 Format of Data Memory Row Address Pointer Address 7AH 7BH 7CH 7EH 7FH Program status word (PSWORD) Index register (IX) Register Memory pointer (MP) IXH Symbol MPH Bit b3 M P E b2 b1 b0 b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 IXM IXL PSW b0 b3 b2 b1 b0 I X E Data memory access Fixed Fixed at at 0 0 MP BANK Row address M P E VRAM access Fixed at 0 MP VRAMBANK Row address 0 0 0 0 0 0 I X E Upon reset Power-on Clock stop CE 0 0 0 0 0 0 51 PD17068 5.7 5.7.1 GENERAL-PURPOSE REGISTER POINTER (RP) Format of General-Purpose Register Pointer Fig. 5-8 shows the format of the general-purpose register pointer. As shown in Fig. 5-8, the general-purpose register pointer consists of 7 bits: the 4 bits of address 7DH (RPH) of the system register, and the higher 3 bits of address 7EH (RPL) of the system register. However, the higher 2 bits of address 7DH are always set to 0, so that the lower 5 bits (lower 2 bits of address 7DH and higher 3 bits of address 7EH) are usable. Fig. 5-8 Format of General-Purpose Register Pointer Address Register Symbol Bit b3 7DH 7EH General-purpose register pointer (RP) RPH b2 b1 b0 b3 RPL b2 b1 b0 M S B L S B B C D Data 0 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 52 PD17068 5.7.2 General-Purpose Register Pointer Functions The general-purpose register pointer specifies a general-purpose register in the data memory. Fig. 5-9 shows the address of a general-purpose register specified with the general-purpose register pointer. As shown in Fig. 5-9, the higher 4 bits (RPH: address 7DH) of the general-purpose register pointer specify a bank, and the lower 3 bits (RPL: address 7EH) of the general-purpose register pointer specify a row address. The effective bits of the general-purpose register pointer are the five bits, so that any row address (0H-7H) of any bank can be specified as a general-purpose register. However, when the VRAMSEL flag (RF: 33H, bit 3) is set to 1, the VRAM area and 40H-6FH of BANK2 cannot be specified as general-purpose registers. See Chapter 6 for details of general-purpose register operation. Fig. 5-9 General-Purpose Register Addresses Specified by General-Purpose Register Pointer General-purpose register pointer (RP) RPH b3 b2 b1 M S B b0 b3 b2 RPL b1 L S B B C D b0 0 0 Specifies a row address. Specifies a bank. Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 BANK0 Row address 0H 1H 2H 3H 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 BANK2 4H 5H 6H 7H 5.7.3 Notes on Using General-Purpose Register Pointer The low-order bit of address 7EH (RPL) of the general-purpose register pointer is used as the BCD flag of the program status word. Pay attention to the value of the BCD flag when rewriting RPL. 53 PD17068 5.8 5.8.1 PROGRAM STATUS WORD (PSWORD) Format of Program Status Word Fig. 5-10 shows the format of the program status word. As shown in Fig. 5-10, the program status word consists of 5 bits: the low-order bit of 7EH (RPL) of the system register, and the 4 bits of address 7FH (PSW) of the system register. A different function is assigned to each bit of the program status word; the program status word consists of a BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Fig. 5-10 Format of Program Status Word Address Register Symbol Bit b3 7EH 7FH Program status word (PSWORD) PSW b0 B C D b3 C M P b2 C Y b1 Z b0 I X E (RP) RPL b2 b1 Data Upon reset Power-on Clock stop CE 0 0 0 0 0 0 54 PD17068 5.8.2 Program Status Word Functions The program status word is used to set conditions for transfer instructions and operations by the arithmetic logic unit (ALU), and also to indicate the states of the results of operations. Table 5-2 outlines the function of each flag of the program status word. See Chapter 7 for details. Table 5-2 Outline of Function of Each Flag of Program Status Word (RP) RPL b3 b2 b1 Program status word (PSWORD) PSW b0 B C D b3 C M P b2 C Y b1 Z b0 I X E Flag name Index enable flag (IXE) Function Used to specify whether a data memory address is to be modified when a data memory manipulation instruction is executed. 0 : Not modified 1 : Modified Used to indicate that the result of an arithmetic operation is 0. Note that the states of 0 and 1 differ, depending on the value of the compare flag. Used to indicate the occurrence of a carry or borrow as the result of an addition or subtraction instruction executed. This flag is reset to 0 when neither a carry nor a borrow is produced. This flag is set to 1 when a carry or borrow is produced. This flag is used also as a shift bit for the RORC r instruction. Used to specify whether to store the result of an arithmetic operation in a data memory area or generalpurpose register. 0 : Stores the result. 1 : Does not store the result. Used to specify whether to perform an arithmetic operation in decimal. 0 : Performs a binary operation. 1 : Performs a decimal operation. Zero flag (Z) Carry flag (CY) Compare flag (CMP) BCD flag (BCD) 55 PD17068 5.8.3 Notes on Using Program Status Word When an arithmetic instruction (addition or subtraction) is executed for the program status word, the result of the arithmetic operation is stored. If an operation is performed which produces the result 0000B with a carry, for example, 0000B is stored in the PSW. 5.9 NOTES ON USING SYSTEM REGISTER Those data items in the program status word that are always set to 0 are not affected by an attempt to execute a write instruction. When those data items in the program status word that are always set to 0 are read, 0 is read. 56 PD17068 6. GENERAL-PURPOSE REGISTER (GR) 6.1 OUTLINE OF GENERAL-PURPOSE REGISTER Fig. 6-1 outlines the general-purpose register. As shown in Fig. 6-1, the general-purpose register consists of a general-purpose register pointer and general-purpose register body. The bank and row address of a general-purpose register body is specified with the general-purpose register pointer. A general-purpose register pointer body is used to perform an operation with or transfer data to and from a data memory area. Fig. 6-1 Outline of General-Purpose Register Column address Data memory Row address General-purpose register pointer General-purpose register Transfer, operation BANK0 BANK1 BANK2 System register 6.2 GENERAL-PURPOSE REGISTER BODY The general-purpose register body consists of a row on the data memory, which is 16 nibbles (16 x 4 bits) long. See Section 5.7 for information about the general-purpose register pointer, and a bank and row address specifiable as a general-purpose register. One instruction can be used to perform an operation with or transfer data to and from a 16-nibble row specified as a general-purpose register. This means that an operation or data transfer between data memory areas can be performed with one instruction. As with other data memory areas, a general-purpose register can be controlled using data memory manipulation instructions. 57 PD17068 6.3 GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS Sections 6.3.1 and 6.3.2 below describe general-purpose register address generation when each instruction is executed. For the detailed operation of each instruction, see Chapter 7. 6.3.1 Addition Instructions (ADD r,m, ADDC r,m) Subtraction Instructions (SUB r,m, SUBC r,m) Logical Operation Instructions (AND r,m, OR r,m, XOR r,m) Direct Transfer Instructions (LD r,m, ST m,r), and Rotate Instruction (RORC r) Table 6-1 indicates a general-purpose register address specified by operand r of an instruction. Operand r specifies only a column address. Table 6-1 General-Purpose Register Address Generation Row address b0 b2 b1 b0 Bank b3 b2 b1 Column address b3 b2 b1 b0 General-purpose register address Contents of generalpurpose register pointer r 6.3.2 Indirect Transfer Instructions (MOV @r,m, MOV m,@r) Table 6-2 indicates a general-purpose register address specified by operand r of an instruction, and an indirect transfer address specified by @r. Table 6-2 General-Purpose Register Address Generation Bank b3 b2 b1 b0 Row address b2 b1 b0 Column address b3 b2 b1 b0 General-purpose register address Contents of generalpurpose register pointer r Same as data memory Indirect transfer address Contents of r 58 PD17068 6.4 6.4.1 NOTES ON USING GENERAL-PURPOSE REGISTER Row Address of General-Purpose Register The row address of a general-purpose register is specified by the general-purpose register pointer. Accordingly, note that the currently specified bank may differ from the bank of the general-purpose register specified. 6.4.2 Operation between General-Purpose Register and Immediate Data No instruction is available for operation between a general-purpose register and immediate data. To execute an operation instruction between a general-purpose register and immediate data, the generalpurpose register area must be handled as a data memory area. 59 PD17068 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK 7.1 OVERVIEW Fig. 7-1 is an overview of the ALU block. As shown in Fig. 7-1, the ALU block consists of the ALU, temporary storage registers A and B, program status word, decimal conversion circuit, and data memory address controller. The ALU performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. Fig. 7-1 Overview of the ALU Block Data bus Address controller Temporary storage register A Temporary storage register B Program status word Detecting a carry, borrow, or zero Setting decimal calculation or result storage ALU * Arithmetic operation * Logic operation * Bit discrimination * Comparative discrimination * Rotation * Transfer Indexing memory pointer Data memory Decimal conversion 60 PD17068 7.2 7.2.1 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 Temporary Storage Registers A and B Temporary storage registers A and B temporarily hold the 4-bit data. These registers are automatically used when an instruction is executed. They cannot be controlled by a program. 7.2.3 Program Status Word A program status word controls the operation of the ALU and holds the status of the ALU. For details of the program status word, see Section 5.8. 7.2.4 Decimal Conversion Circuit If the BCD flag of the program status word is set to 1 when an arithmetic operation is executed, the decimal conversion circuit converts the results of the arithmetic operation to a decimal number. 7.2.5 Address Controller The address controller specifies an address in data memory. At the same time, the circuit also controls address modification by the index register or data memory row address pointer. 7.3 ALU OPERATIONS Table 7-1 lists the operations performed by the ALU when instructions are executed. Table 7-2 shows the data memory address modification by the index register and data memory row address pointer. Table 7-3 lists the converted decimal data used in decimal operations. 61 PD17068 Table 7-1 ALU Operations ALU function Operation difference due to program status word (PSWORD) Instruction Value Value of the of the BCD flag CMP flag 0 0 Operation Binary operation The result is stored. Binary operation The result is not stored. Decimal operation The result is stored. Decimal operation The result is not stored. Set by a carry or borrow. Otherwise, the flag is reset. Operation of the CY flag Operation of the Z flag Set if the operation result is 0000B. Otherwise, the flag is reset. Retains the status if the operation result is 0000B. Otherwise, the flag is reset. Set if the operation result is 0000B. Otherwise, the flag is reset. Retains the status if the operation result is 0000B. Otherwise, the flag is reset. Address modification Index Memory pointer r, m Addition ADD m, #n4 r, m ADDC m, #n4 Subtraction r, m SUB m, #n4 r, m SUBC m, #n4 r, m Logic operation OR m, #n4 r, m AND m, #n4 r, m XOR m, #n4 Discrimination 0 1 Provided Not provided 1 0 1 1 Optional Optional Not changed (hold) (hold) Retains the previous state. Retains the previous state. Provided Not provided SKT SKF SKE SKNE SKGE SKLT LD m, #n m, #n m, #n4 Optional Optional Not changed (hold) (reset) Retains the previous state. Retains the previous state. Provided Not provided Comparison m, #n4 Optional Optional Not changed (hold) (hold) m, #n4 m, #n4 r, m m, r Optional Optional Not changed (hold) m, #n4 (hold) @r, m m, @r Retains the previous state. Retains the previous state. Provided Not provided Transfer ST Retains the previous state. Retains the previous state. Provided Not provided MOV Provided Value of b0 of the generalpurpose register Rotation RORC r Optional Optional Not changed (hold) (hold) Retains the previous state. Not Not provided provided 62 PD17068 Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register and Data Memory Row Address Pointer General-purpose register address specified with r IXE MPE Bank Row address Column address Data memory address specified with m Bank Row address Column address Indirect transfer address specified with @r Bank Row address Column address b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 0 0 RP r BANK m BANK mR (r) 0 1 Same as above Same as above MP (r) 1 0 Same as above BANK Logical IX OR m BANK mR OR (r) Logical IXH, IXM 1 1 Same as above Same as above MP (r) BANK IX IXE : Bank register : Index register : Index enable flag IXH : Bits 10 to 8 of the index register IXM : Bits 7 to 4 of the index register IXL m mR mC MP r RP (x) : Bits 3 to 0 of the index register : Data memory address specified with mR and mC : Data memory row address (high order) : Data memory column address (low order) : Data memory row address pointer : General-purpose register column address : General-purpose register pointer : Contents addressed by x x : m, r, and other direct address MPE : Memory pointer enable flag 63 PD17068 Table 7-3 Converted Decimal Data Operation result Hexadecimal addition CY Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal addition CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1010B 1011B 1100B 1101B Operation result Hexadecimal subtraction CY Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal subtraction CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Remark Correct decimal conversion is not possible in the shaded area. 64 PD17068 7.4 7.4.1 NOTES ON USING THE ALU Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. The CY and Z flags of the program status word are usually set or reset according to the result of the arithmetic operation. If the arithmetic operation is performed on the program status word itself, the result of the operation is stored and a carry, borrow, or zero cannot be discriminated. If the CMP flag is set, the result of the arithmetic operation is not stored and the CY and Z flags are set or reset as usual. 7.4.2 Notes on Performing Decimal Operations A decimal operation can be carried out only when the operation result is within the following ranges: (1) The result of addition is between 0 and 19 in decimal. (2) The result of subtraction is between 0 and 9 or -10 and -1 in decimal. If a decimal operation exceeding the above ranges is performed, the CY flag is set, resulting in a value greater than or equal to 1010B (0AH). 65 PD17068 8. REGISTER FILE (RF) 8.1 OVERVIEW Fig. 8-1 shows an overview of the register file. As shown in Fig. 8-1, the register file consists of control registers in a different space from data memory, and a part of data memory. The control register sets the conditions of the peripheral hardware. The data in the register file is read and written through a window register. Fig. 8-1 Overview of the Register File Register file 0 Peripheral hardware 1 Control registers (different space from data memory) 2 3 Row address 4 (Configured in data memory) Data manipulation through the window register 5 6 7 System register Window register 66 PD17068 8.2 CONFIGURATION AND FUNCTIONS OF THE REGISTER FILE Fig. 8-2 shows the configuration of the register file and the relationship between the register file and data memory. Like data memory, the register file is assigned addresses in units of four bits. The row addresses range from 0H to 7H and the column addresses from 0H to 0FH, that is, 128 nibbles in total. The address locations from 00H to 3FH are referred to as control registers and are used to set the conditions for the peripheral hardware. Address locations 40H to 7FH and data memory overlap. The data at addresses 40H to 7FH in the register file is identical to that at addresses 40H to 7FH in the current bank of data memory. Because address locations 40H to 7FH and data memory overlap, they are the same as the ordinary address locations in data memory, except that they can be manipulated by the register file manipulation instructions (PEEK WR, rf and POKE rf, WR). Fig. 8-2 Configuration of the Register File and the Relationship between the Register File and Data Memory Column address 0 0 1 2 Row address 3 4 5 BANK0 6 7 BANK1 BANK2 Data memory 1 2 3 4 5 6 7 8 9 A B C D E F System register 0 1 2 3 Register file Control register 67 PD17068 8.2.1 Register File Manipulation Instructions (PEEK WR, rf and POKE rf, WR) Data in the register file is read and written through the window register of the system register. The following instructions are used: (1) PEEK WR, rf Reads the data at address rf of the register file into the window register. (2) POKE rf, WR Writes the data of the window register at address rf into the register file. 8.3 CONTROL REGISTERS Fig. 8-3 shows the configuration of the control registers. As shown in Fig. 8-3, the control registers consist of 64 nibbles (64 x 4 bits) of addresses 00H to 3FH in the register file. However, only 61 nibbles are actually used. The remaining three nibbles are not used, reading and writing for these nibbles being inhibited. Each nibble of each control register has an attribute. Each nibble has one of the following four attributes: read/write (R/W), read only (R), write only (W), and reset at reading (R & Reset). If writing to a read-only (R, or R & Reset) register is attempted, nothing changes. If reading from a write-only (W) register is attempted, an undefined value is read. Of the four bits in a single nibble, a bit that is always set to 0 is always read as 0. Even if writing is attempted, the bit remains set to 0. If an attempt is made to read the contents of the three unused nibbles, an undefined value is read. If writing to the unused part is attempted, nothing changes. 68 PD17068 [MEMO] 69 PD17068 Fig. 8-3 Configuration of the Control Registers (1/2) Column Address Row Address Item 0 1 2 3 PWM mode select register 3 P W M 8 0S E L 4 5 6 7 Register Stack pointer CE pin edge detection (SP) register ( S P 3 ( S P 2 ( SS PP 10 0 0 ( PWM mode PWM mode Watch timer CE pin level select select mode select judge register register 2 register 1 register P W M 7 S E L P W M 6 S E L P W M 5 S E L P W M 4 S E L P W M 3 S E L P W M 2 S E L P W M 1 S E L P W M 0 S E L W CX T KT M OS H SE L0EL0 D L C E 0 0 0 (8)Note Symbol C E E D 0E00 T Read/ Write R/W R & Reset R/W R/W R/W W R / W R Register PLL referHSYNCHSYNCence counter-gate counter-gate clock select judge control register register register H S C G 0T 1 H S C G T 0 H S C G O0 S T T R P L L R F C K 3 P L L R F C K 2 P L L R F C K 1 Watch timer INTNC mode Basic timer 1 Basic timer 0 select carry flip-flop carry flip-flop reset register register judge register judge register I N T N C0 M D 0 B T M 1 0C0 Y B T M 0 0C Y 1 (9)Note Symbol 0 0 0 P WWWW II LTTTT NN L MMMM TT RRRRR NN FEEEE0CC CSSSS MM K3210 DD 0 21 R/W A/D converter control register A D C E N0 A D C C 0M P R/W 0 0 Read/ Write Clock-stop release enable register R/W R/W R & Reset Port 2D bit I/O select register P 2 D B 0I O 2 P 2 D B I O 1 R & Reset Port 1C group I/O select register P 1 C G 0I O Register A/D converter PLL-unlockflip-flop channel select judge register register P L L U 0L 2 (A)Note Symbol 0 0 R AAA L DDD S CCC E CCC 0N0HHH0 210 0 P 2 D B I0 O 0 0 Read/ Write R/W IDC background select register I D C B K R I D C B K G R/W IDC enable register R & Reset PLL-unlockflip-flop sensibility select register P L U L S E N 1 P L U L S E N 0 IDC mode select register V R A M S E L I D C S E L I D C D 1 4 S L R/W P1B2 pin edge detection register R Port 1B bit I/O select register P 1 B 2 E D E T P 1 B B I O 3 P 1 B B I O 2 P 1 B B I O 1 P 1 B B I O 0 R/W Port 0B bit I/O select register P 0 B B I O 3 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 R/W Port 0A bit I/O select register P 0 A B I O 3 P 0 A B I O 2 P 0 A B I O 1 P 0 A B I O 0 Register 3 (B)Note I D C B Symbol K E N I D C B K0 B 0 0 I D C E N0 0 I D C C P0 C H 0 0 Read/ Write R/W R/W R /W R/W R & Reset R/W R/W R/W Note An address used with the assembler (AS17K) is indicated in parentheses. 70 PD17068 Fig. 8-3 Configuration of the Control Registers (2/2) 8 Serial I/O 0 mode select register 9 Timer 0 clock select register T M 0 C 0K A B C D Timer 0 control register E Timer 0 overflow register T M 0 V 0F0 F Interrupt group selection register I G R P 01 S L I G R P 0 S L Basic timer 2 Basic timer 1 Basic timer 0 mode select mode select clock select register register register B T M 2 E X C K B T M 2 Z X B T M 2 C K 1 B T M 2 C K 1 B T M 1 E X C K B T M 1 Z X B T M 1 C K 1 B T M 1 C0 K 0 B T M 0 0C K 1 SSSS IBII O OO 0 00 C MT0 H SX 0 B TTT T MMM M 00O 0 RRE C0PEN0 K TS 0 R R/W W / W 0 R/W Serial I/O 0 wait control register SSSS BIII AOOO C000 K NWW WR R TQQ 10 R/W Serial I/O 0 status judge register S I O 0 S F 8 S I O 0 S F 9 S B S T T R/W R/W Timer 1 clock select register T M 1 C 0K 1 T M 1 C K0 0 R/W Timer 1 control register T M 1 R 0E S T M 1 E N R/W R R/W Interrupt edge selection register III EEE GGG G0N R C P 1 Serial I/O 1 Watch timer Watch timer mode select 8-Hz carry 128-Hz carry register register register S I O 1 T S S I O 1 H I Z S I O 1 C K 1 S I O 1 C0 K 0 W T M 8 0H0 Z 0 0 0 W T M 1 020 8 H Z R/W Interrupt request register 10 I R Q G 0R0 P 0 Interrupt request register 9 R R/W W / W Interrupt request register 8 I R Q S I O 0 R/W Interrupt request register 7 I N T G R0 P 1 R & Reset Interrupt enable register 3 R & Reset Interrupt enable register 2 I P G R P 1 I P I D C V P I P B T M 2 R/W Interrupt enable register 1 I P T M 1 III PPP T0N M C 0 S B B S Y0 0 0 I R Q S 0I0 O 1 0 0 0 I R Q G R0 P 1 III PPP GSS RII 0POO 010 R R/W R/W Interrupt request register 6 R/W Interrupt request register 5 R R/W R/W Interrupt request register 3 R/W Interrupt request register 2 R/W Interrupt request register 1 I R Q N 0C Serial I/O 0 Serial I/O 0 interrupt clock select mode register register S I O 0 0I M D 1 R/W S I O 0 I0 M D 0 S I O 0 0C K 1 Interrupt request register 4 0 S I O 0 C0 K 0 I R Q I 00D0 C V P R/W 0 I R Q B 0T0 M 2 0 I R Q T 0M00 1 II II RN RN QT QT T0 0N 0M 00 C0 0 R/W R/W R/W R/W R R/W R R/W 71 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (1/7) Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 (SP3) Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Set value Function overview 0 Stack (SP2) Stack pointer (SP) 01H R/W (SP1) (SP0) WTMHLD Watch timer mode register W 06H CKOSEL R/W XTSEL 0 0 Timer 0 clock select register 09H R/W 0 TM0CK BTM2EXCK Basic timer 2 mode select register BTM2ZX 0AH R/W BTM2CK1 Sets an interrupt time. BTM2CK0 BTM1EXCK Basic timer 1 mode select register BTM1ZX 0BH R/W BTM1CK1 Sets a carry flip-flop time. BTM1CK0 0 Always set to 0. Basic timer 0 mode select register 0 0CH R/W BTM0CK1 Sets a carry flip-flop time. BTM0CK0 0 Timer 0 control register 0DH R/W TM0RPT W R/W TM0RES TM0EN 0 Timer 0 overflow register 0 0EH R 0 TM0OVF WTMRES3 Watch timer reset register WTMRES2 14H R/W WTMRES1 WTMRES0 Selects whether to reset the watch timer. Does not reset. Resets. 0 H H Detects whether the timer 0 counter overflows. Does not overflow. Overflows. Always set to 0. 0 0 H Always set to 0. Selects the operation mode of timer 0. Selects whether to reset the timer 0 counter. Selects whether to start the timer 0 counter. Free-run count mode Does not perform reset. Does not start. Modulo count mode Resets. Starts. 0 0 100 ms 0 0 5 ms 0 0 1 ms 0 0 1 ms 0 0 H Selects the base clock (internal/ external). Turns the zero-cross circuit on or off. Sets the clock of timer 0. Selects the base clock (internal/ external). Turns the zero-cross circuit on or off. 10 s 50 s Always set to 0. 0 0 H 0 Selects whether to hold the watch timer for 500 ms. Always set to 0. Selects whether to output an Outputs. oscillation frequency of 32.768 kHz. Does not output. Selects the function of the Operates as a port. Connects an P0D1 and P0D0 pins. oscillator. 0 0 0 Does not hold. Holds. H H Stack pointer 12 12 12 H H 0, 4: 100 ms 1,5: 5 ms 2,6: 1 ms 3,7: 125 s 8, 9: Divides the external clock by 5. A, B: Divides the external clock by 6. C, D: Divides the external clock by 5 0 (with zero-cross on). E, F: Divides the external clock by 6 (with zero-cross on). 0, 4: 100 ms 1,5: 5 ms 2,6: 1 ms 3,7: 125 s 8, 9: Divides the external clock by 5. A, B: Divides the external clock by 6. C, D: Divides the external clock by 5 0 (with zero-cross on). E, F: Divides the external clock by 6 (with zero-cross on). 0 H 0 H Timer 0 0 H Remark H: Holds the previous state. 72 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (2/7) Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 0 Basic timer 1 carry flip-flop judge register R& RES 0 0 BTM1CY 0 Basic timer 0 carry flip-flop judge register R& RES 0 0 BTM0CY 0 Always set to 0. Timer 1 clock select register 0 1AH R/W TMCK1 Always set to 0. Always set to 0. Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Set value Function overview 0 16H 0 Detects the status of the carry flip-flop. 1 1 Reset Set 17H 0 Detects the status of the carry flip-flop. 1 1 Reset Set 0 Sets the clock of timer 1. 0 1 ms 0 0 100 s 1 1 50 s 0 1 10 s 1 0 H Timer TMCK0 0 R/W Timer 1 control register 0 1BH W R/W TM1RES TM1EN 0 Watch timer 8-Hz carry register R& RES 0 0 WTM8HZ 0 Watch timer 128-Hz carry register R& RES 0 0 WTM128HZ 0 Always set to 0. Interrupt group selection register 0 0FH R/W IGRP1SL IGRP0SL 0 Selects an interrupt source (group 1). Timer 0 overflow interrupt (group 0) Always set to 0. Detects the status of the carry flip-flop. Always set to 0. Detects the status of the carry flip-flop. Always set to 0. Selects whether to reset the timer 1 counter. Selects whether to operate the timer 1 counter. Always set to 0. Does not perform reset. Does not start. 0 Resets. Starts. 0 H 1DH 0 H H Reset Set 1EH 0 H H Reset Set 0 VSYNC signal Is not used. HSYNC signal Is used. 0 0 Interrupt INTNC mode select register INTNCMD2 15H R/W INTNCMD1 INTNCMD0 0 Always set to 0. Sets the edge where an interrupt is issued (group 1). Sets the edge where an interrupt is issued (INT0). Sets the edge where an interrupt is issued (INTNC). Selects the pulse width used for accepting the interrupt of the INTNC pin. 0 : Accepts at the edge. 2 : 400 s 4 : 4 ms 1 : 200 s 3 : 2 ms 0 0 0 Interrupt edge selection register IEGGRP1 1FH R/W IEG0 IEGNC 0 Rising edge Falling edge 0 0 Remark H: Holds the previous state. 73 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (3/7) Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 0 Interrupt request register 10 0 29H R/W 0 Always set to 0. Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Set value Function overview 0 Low level High level 0 0 0 Detects no interrupt request IRQGRP0 0 Interrupt request register 9 0 2AH R/W 0 IRQSIO1 0 Interrupt request register 8 0 2BH R/W 0 IRQSIO0 R Interrupt request register 7 INTGRP1 0 2CH R/W 0 Detects an interrupt request (group 0). or interrupt handling is in progress. Detects an interrupt request. Always set to 0. 0 Detects no interrupt request or interrupt handling is in progress. 0 0 Detects an interrupt request (SIO1). Detects an interrupt request. Always set to 0. 0 Detects no interrupt request or interrupt handling is in progress. 0 0 Detects an interrupt request (SIO0). Displays the level of the HSYNC/VSYNC signal. Always set to 0. Detects an interrupt request. Low level High level 0 Detects no interrupt request 0 0 IRQGRP1 0 Interrupt Displays an interrupt request (group 1). or interrupt handling is in progress. Detects an interrupt request. Interrupt request register 6 0 3AH R/W 0 IRQIDCVP 0 Always set to 0. 0 Detects no interrupt request or interrupt handling is in progress. 0 0 Detects an interrupt request (VRAM pointer). Detects an interrupt request. Interrupt request register 5 0 3BH R/W 0 IRQBTM2 0 Always set to 0. 0 Detects no interrupt request or interrupt handling is in progress. 0 0 Detects an interrupt request (BTM2). Detects an interrupt request. Interrupt request register 4 0 3CH R/W 0 Always set to 0. 0 Detects no interrupt request 0 0 IRQTM1 0 Interrupt request register 3 0 3DH R/W 0 Detects an interrupt request (TM1). or interrupt handling is in progress. Detects an interrupt request. Always set to 0. 0 Detects no interrupt request 0 0 IRQTM0 R Interrupt request register 2 INT0 0 3EH R/W 0 Detects an interrupt request (TM0). or interrupt handling is in progress. Detects an interrupt request. Displays the level of the signal input to the INT0 pin. Always set to 0. Low level High level 0 Detects no interrupt request 0 0 IRQ0 Detects an interrupt request (INT0 pin). or interrupt handling is in progress. Detects an interrupt request. 74 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (4/7) Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 R Interrupt request register 1 3FH R/W INTNC 0 0 IRQNC 0 Always set to 0. Interrupt enable register 3 0 2DH R/W IPGRP0 Group 0 IPSI01 Serial interface 1 IPSIO0 Interrupt enable register 2 IPGRP1 2EH R/W IPIDCVP IPBTM2 IPTM1 Timer 0 Interrupt enable register 1 IPTM0 2FH R/W IP0 IPNC 0 CE pin edge detection register R& RES 0 0 CEEDET 0 CE pin level judge register 0 07H R 0 Always set to 0. Always set to 0. INT0 pin INTNC pin Serial interface 0 Group 1 VRAM pointer Basic timer 2 Timer 1 Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Function overview Set value 0 Displays the level of the signal input to the INTNC pin. Always set to 0. Detects an interrupt request (INTNC pin). Detects no interrupt request or interrupt handling is in progress. Low level High level 0 0 0 Detects an interrupt request. 0 0 0 Interrupt Selects whether to enable an interrupt. Inhibits an interrupt. Enables an interrupt. 0 0 0 0 0 0 02H 0 Does not detect the input. - - Detects the input of a rising edge to the CE pin. Detects the input. 0 - - Pin CE 0 Clock-stop release enable register 0 20H R/W 0 RLSEN 0 P1B2 pin edge detection register R& RES 0 0 P1B2EDET Detects the status of the CE pin. Low level High level Always set to 0. 0 Selects whether to release the clock-stop by the P1B2 pin. H H Does not release. Releases. Always set to 0. 0 Detects the input of a rising edge to the P1B2 pin. Does not detect the input. - - 34H Detects the input. PLL frequency synthesizer PLLRFCK3 2: 5 kHz 3: 10 kHz 4: 6.25 kHz 5: 12.5 kHz PLL reference clock select register PLLRFCK2 13H R/W PLLRFCK1 PLLRFCK0 Sets the PLL reference frequency. 6: 25 kHz F: Operation stop (disable status) 0, 1, 7 to E: Setting inhibited F F H Remark H: Holds the previous state. 75 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (5/7) Peripheral hardware Control register b3 b2 b1 b0 Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Register Address Read/ Write Symbol Function overview Set value 0 0 PLL frequency synthesizer PLL-unlockflip-flop judge register 22H R& RES 0 0 PLLUL 0 Always set to 0. UH Detects the status of the unlock flip-flop. Always set to 0. H Lock status Unlock status PLL-unlockflip-flop sensibility select register 0 32H R/W PLULSEN1 PLULSEN0 0 Specifies a delay for setting the unlock flip-flop. Always set to 0. 1 : P0D0/ADC1/XTOUT 0 : ADC0 2 : P0D1/ADC2/XTIN 3 : P0D2/ADC3 4 : P0D3/ADC4 5 : P0D0/ADC5 6 : P0C1/ADC6 6 : P0D2/ADC7 Stop Start 0 Always set to 0. 0 R ADCCMP 0 Detects the result of comparison. Always set to 0. P2D2 pin P2D1 pin P2D0 pin VADCIN < VREF VADCIN > VREF UH H 0 0 01.25 03.5 00.25 1Disable 0 0 H 0-1.5 s 1-3.75 s 1-0.5 s 1Disable A/D converter A/D converter channel select register ADCCH2 21H R/W ADCCH1 ADCCH0 ADCEN Sets the operation of the A/D converter. Selects the pins to be used as the A/D converter. 0 0 0 A/D converter control register R/W 24H 0 Port 2D bit I/O select register P2DBIO2 26H R/W P2DBIO1 P2DBIO0 0 Sets the pin for input or output (bit I/O). 0 Input Output 0 0 Port 1C group I/O select register 0 27H R/W 0 P1CGIO Always set to 0. 0 0 0 Sets port 1C for input or output (group I/O). Input Output General-purpose port P1BBIO3 Port 1B bit I/O select register P1BBIO2 35H R/W P1BBIO1 P1BBIO0 P1B0 pin P0BBIO3 Port 0B bit I/O select register P0BBIO2 36H R/W P0BBIO1 P0BBIO0 P0ABIO3 Port 0A bit I/O select register P0ABIO2 37H R/W P0ABIO1 P0ABIO0 P0B3 pin P0B2 pin P0B1 pin P0B0 pin P0A3 pin P0A2 pin P0A1 pin P0A0 pin Sets the pin for input or output (bit I/O). Input Output 0 0 0 P1B3 pin P1B2 pin P1B1 pin Remark H: Holds the previous state. 76 U: Undefined PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (6/7) Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 0 0 PWM mode select register 3 03H R/W 0 PWM8SEL PWM7SEL PWM mode select register 2 PWM6SEL 04H R/W PWM5SEL PWM4SEL PWM3SEL PWM2SEL PWM mode select register 1 05H R/W PWM1SEL PWM0SEL SIO0CH Serial I/O 0 mode select register SB 08H R/W SIO0MS SIO0TX SBACK Serial I/O 0 wait control register SIO0NWT 18H R/W SIO0WRQ1 Sets a wait mode. SIO0WRQ0 SIO1TS Serial I/O 1 mode select register SIO1HIZ 1CH R/W SIO1CK1 Sets the I/O clock. SIO1CK0 SIO0SF8 Serial I/O 0 status judge register SIO0SF9 28H R SBSTT SBBSY 0 Always set to 0. Serial I/O 0 interrupt mode register 0 38H R/W SIO0IMD1 SIO0IMD0 0 Always set to 0. Serial I/O 0 clock select register 0 39H R/W SIO0CK1 SIO0CK0 P2A0/PWM8 pin P2B3/PWM7 pin P2B2/PWM6 pin P2B1/PWM5 pin P2B0/PWM4 pin P2C3/PWM3 pin P2C2/PWM2 pin P2C1/PWM1 pin P2C0/PWM0 pin Always set to 0. Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Function overview Set value 0 D/A converter Selects whether to set these pins as a D/A converter. 0 0 U General-purpose output port DA converter Sets the number of communication wires. Sets the communication method. Sets master or slave operation. Sets the direction of transfer. Sets and detects the acknowledgment (I2C bus method). Selects whether to enable a wait. Two-wire system Serial I/O method Master operation Reception Three-wire system I2C bus method (twowire system only) 0 Slave operation Transmission 0 0 Sets and detects 0 or 1. Enables. Releases. 0 0 No 0 Data 1 Acknow- 1 Address ledge 1 wait. 0 wait. 1 wait. 0 wait. Stops the operation. General-purpose I/O port 0 0 Starts the operation Serial data output pin 0 1 1 0 0 0 0 Selects whether to start or stop the operation. Sets the status of the P2D1/SO1 pin. Serial interface External 100 kHz 500 kHz 1 kHz 0 clock 1 0 1 0 or 1 0 or 1 8 9 0 0 0 Detects the contents of the clock counter. Detects the number of clocks (I2C bus method). Detects the starting conditions (I2C bus method). Up to nine clocks are set, beginning with the start condition. All clocks are set, from the start condition up to the stop condition. Sets the interrupt condition of serial interface 0. 7th clock 0 Seventh 0 Eighth 1 after the 1 Stop condistart con0 clock 1 clock 0 dition 1 tion U H H U Sets the internal clock of serial interface 0. 0 100 kHz 0 1 0 50 kHz 0 1 500 kHz 1 1 1 kHz H H Remark H: Holds the previous state. U: Undefined 77 PD17068 Table 8-1 Peripheral Hardware Control Functions of the Control Registers (7/7) Horizontal synchronizing signal counter Peripheral hardware Control register b3 Register Address Read/ Write b2 b1 b0 0 HSYNC-counter -gate control register 0 11H R/W HSCGT1 HSCGT0 HSCGOSTT HSYNC-countergate judge register 0 12H R 0 0 IDCBKEN IDC background select register IDCBKR 30H R/W IDCBKG IDCBKB 0 Background color G Background color B Always set to 0. Symbol Peripheral hardware control function Upon reset P o w e r 1 o n S T O P C E Function overview Set value 0 Always set to 0. 0 Controls the gate of the HSYNC counter. Detects whether the gate of the HSYNC counter is open or closed. 0 Gate 0 Gate 1 1.69 ms 1 Setting 1 inhibited 0 closed 1 open 0 open Closed Open 0 0 0 - - Specifies the screen background. Background color R Eight colors Does not display the Displays the screen screen background color. background color. 0: Black, 1: Blue, 2: Green, 3: Cyan, 4: Red, 5: Magenta, 6: Yellow, 7: White 0 0 0 IDC IDC enable register 0 31H R/W 0 IDCEN VRAMSEL IDCISEL Always set to 0. 0 Turns the IDC display on or off. Turns VRAM on or off. Display on VRAM off Display off VRAM on 0 0 IDC mode select register 33H R/W IDCD14SEL IDCCPCH Selects the function of the General-purpose port I pin P0B2/I pin. Sets the number of dots in the vertical 14 dots direction for the character to be displayed. 16 dots Sets the display interval between No interval Interval of 2 dots characters. 0 0 0 78 PD17068 8.4 NOTES ON USING THE REGISTER FILE When operating a write-only (W) register, read-only (R) register, or unused register of the control registers (address locations 00H to 3FH of the register file), note (1), (2), and (3) below: (1) If reading from a write-only register is attempted, an undefined value is read. (2) If writing to a read-only register is attempted, nothing changes. (3) If an attempt is made to read the contents of an unused part, an undefined value will be read. If writing to an unused part is attempted, nothing changes. 79 PD17068 9. DATA BUFFER (DBF) 9.1 OVERVIEW Fig. 9-1 shows an overview of the data buffer. The data buffer is configured in data memory. It provides the following two functions: (1) Function to read constant data related to program memory (refer to the table) (2) Function to transfer data to or from the peripheral hardware Fig. 9-1 Overview of the Data Buffer Data buffer Writing data (PUT) Referencing a table (MOVT) Reading data (GET) Peripheral hardware Constant data Program memory 80 PD17068 9.2 9.2.1 DATA BUFFER MAIN BODY Configuration of the Data Buffer Main Body Fig. 9-2 shows the configuration of the data buffer. As shown in Fig. 9-2, the data buffer consists of 16 bits of addresses 0CH to 0FH of BANK0 in data memory. The most significant bit (MSB) of the 16-bit data is bit 3 at address 0CH. The least significant bit (LSB) is bit 0 at address 0FH. The data buffer is configured in data memory and can thus be manipulated by any data memory manipulation instruction. Fig. 9-2 Configuration of the Data Buffer Column address 0 0 1 2 Low address 3 4 5 6 7 7 7 BANK0 BANK1 BANK2 System register Data memory 1 2 3 4 5 6 7 8 9 A B C D E F Data buffer (DBF) Address Data memory Bit Bit Symbol M S B Data buffer Data 0CH 0DH 0ED 0FH b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBF 3 DBF 2 DBF 1 DBF 0 L S B Data 81 PD17068 9.2.2 Instruction to Reference a Table (MOVT DBF, @AR) The MOVT DBF, @AR instruction functions as described below: When an instruction to reference a table is executed, a stack of a single level is used. All program memory addresses, 0000H to 2FFFH, allow table reference. MOVT DBF, @AR Data at the address specified by the address register is read from program memory and placed in the data buffer. 9.2.3 Instructions for Controlling the Peripheral Hardware (PUT, GET) The PUT and GET instructions operate as described below: (1) GET DBF, p Data in the peripheral register at address p is read and written into the data buffer. (2) PUT p, DBF Data in the data buffer is set in the peripheral register at address p. 9.3 PERIPHERAL HARDWARE AND DATA BUFFER Table 9-1 lists the functions of the data buffer and peripheral hardware. 82 PD17068 [MEMO] 83 PD17068 Table 9-1 Relationship between the Peripheral Hardware and Data Buffer (1/2) Peripheral register used to transfer data to or from the data buffer Peripheral hardware Name IDC start position setting register VRAM pointer buffer VRAM VRAM pointer register A/D converter A/D converter data register IDCVPR ADCR 43H 02H PUT/GET PUT/GET Symbol IDCORG IDCVP Peripheral address 01H 42H Instruction that can be used PUT/GET GET IDC Image display controller (IDC) Serial interface 0 (SIO0) Serial interface Serial interface 1 (SIO1) Horizontal synchronizing signal counter Timer 1 modulo Timer 1 Timer 1 counter P2C0/PWM0 pin P2C1/PWM1 pin P2C2/PWM2 pin D/A converter (PWM output) P2C3/PWM3 pin P2B0/PWM4 pin P2B1/PWM5 pin P2B2/PWM6 pin P2B3/PWM7 pin P2A0/PWM8 pin Seconds counter Minutes counter Watch timer Hours counter Days counter Address register (AR) PLL frequency synthesizer Timer 0 Timer 0 modulo Timer 0 counter SIO0 shift register SIO0SFR 03H PUT/GET SIO1 shift register HSYNC counter data register Timer 1 modulo register Timer 1 counter PWM data register 0 PWM data register 1 PWM data register 2 PWM data register 3 PWM data register 4 PWM data register 5 PWM data register 6 PWM data register 7 PWM data register 8 Seconds setting register Minutes setting register Hours setting register Days setting register Address register PLL data register Timer 0 modulo register Timer 0 counter SIO1SFR HSC TM1M TM1C PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5 PWMR6 PWMR7 PWMR8 WTMSEC WTMMIN WTMHR WTMDAY AR PLLR TMOM TMOC 07H 04H 05H 06H 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1AH 1BH PUT/GET 1CH 1DH 40H 41H 46H 47H PUT/GET PUT/GET PUT/GET GET PUT/GET GET PUT/GET GET 84 PD17068 Table 9-1 Relationship between the Peripheral Hardware and Data Buffer (2/2) Function Number of I/O bits of the data buffer 8 16 16 8 Number of bits actually used 8 10 10 6 Description Sets the display start position of the image display controller. Specifies a VRAM address. Reads the value of the VRAM pointer. Sets the reference voltage (VREF) of the A/D converter. VREF = x - 0.5 x VDD, 64 1 x 63 8 8 Sets the serial out data and reads the serial in data. 8 8 8 6 8 8 Reads the value of the horizontal synchronizing signal counter. Sets the reference data for timer 1. Reads the count for timer 1. Sets the duty cycle of the output signal of the D/A converter. 8 8 Duty cycle : D = x x 100%, 0 256 x 255 Frequency : f = 1.953 kHz 6 8 5 3 16 16 16 16 14 16 12 12 Transfers data to or from the address register. Sets N, by which the PLL frequency is divided. Sets the reference data for timer 0. Reads the data of the timer 0 counter. Writes and reads the data of the seconds counter, minutes counter, hours counter, and days counter. 85 PD17068 9.4 NOTES ON USING THE DATA BUFFER When transferring data, through the data buffer, to or from the peripheral hardware, note the following three points on unused peripheral addresses, write-only peripheral registers (PUT only), and read-only peripheral registers (GET only): (1) If reading of a write-only register is attempted, an undefined value will be read. (2) If writing to a read-only register is attempted, nothing changes. (3) If an attempt is made to read the data at an unused address, an undefined value will be read. If writing to the unused address is attempted, nothing changes. 86 PD17068 10. GENERAL-PURPOSE PORTS A general-purpose port outputs high, low, and floating signals to external circuits and reads high and low signals from the external circuits. 10.1 OVERVIEW Table 10-1 indicates the relationship between the ports and port registers. General-purpose ports are classified into three types: I/O ports, input ports, and output ports. I/O ports can be divided into two types: In a bit I/O port, each bit (each pin) can be set to input or output mode. In a group I/O port, the bits can set to input or output mode in units of four bits (four pins). Table 10-1 Relationship between Ports (Pins) and Port Registers (1/2) Pin Port No. Symbol I/O Bank 36 Port 0A 37 38 39 32 33 Port 0B 34 35 48 49 Port 0C 50 51 57 58 Port 0D 59 60 P0D1 P0D0 P0C1 P0C0 P0D3 P0D2 Input 73H P0B1 P0B0 BANK0 P0C3 P0C2 Output 72H P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 I/O (bit I/O) 71H I/O (bit I/O) 70H Address Data setting method Port register (data memory) Symbol Bit symbol (reserved word) b3 b2 P0A b1 b0 b3 b2 P0B b1 b0 b3 b2 P0C b1 b0 b3 b2 P0D b1 b0 P0D1 P0D0 P0C1 P0C0 P0D3 P0D2 P0B1 P0B0 P0C3 P0C2 P0A1 P0A0 P0B3 P0B2 P0A3 P0A2 Remarks 87 PD17068 Table 10-1 Relationship between Ports (Pins) and Port Registers (2/2) Pin Port No. Symbol I/O Bank 15 Port 1A 16 17 18 11 12 Port 1B 13 14 53 54 Port 1C 55 56 6 7 Port 0D 8 9 P1D1 P1D0 P1C1 P1C0 P1D3 P1D2 Output 73H P1B1 P1B0 BANK1 P1C3 P1C2 I/O (group I/O) 72H P1A3 P1A2 Output P1A1 P1A0 P1B3 P1B2 I/O (bit I/O) 71H 70H Address Data setting method Port register (data memory) Symbol Bit symbol (reserved word) b3 b2 P1A b1 b0 b3 b2 P1B b1 b0 b3 b2 P1C b1 b0 b3 b2 P1D b1 b0 b3 P1D1 P1D0 -- -- -- P2A0 P2B3 P2B2 P2B1 P2B0 P2C3 P2C2 P2C1 P2C0 -- P2D2 P2D1 P2D0 Always set to 0 Always set to 0 P1C1 P1C0 P1D3 P1D2 P1B1 P1B0 P1C3 P1C2 P1A1 P1A0 P1B3 P1B2 P1A3 P1A2 Remarks No relevant pins Port 2A 19 40 41 Port 2B 42 43 44 45 Port 2C 46 47 P2C1 P2C0 No relevant pins 20 Port 2D 21 22 P2D1 P2D0 P2D2 I/O (bit I/O) 6FH P2D P2B1 P2B0 BANK2 P2C3 P2C2 Output 72H P2C P2A0 P2B3 P2B2 Output 71H P2B 70H Output P2A b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 88 PD17068 10.2 10.2.1 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C, P2D) Configurations of the I/O ports (1) to (5) below describe the configurations of the I/O ports: (1) P0A (P0A3, P0A2), P0B (P0B2, P0B0), P1B (P1B2, P1B1, P1B0), P2D (P2D2, P2D1, P2D0) I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction RES signal 89 PD17068 (2) P1C (P1C3, P1C2/ADC7, P1C1/ADC6, P1C0/ADC5) I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction A/D converter channel select signal (active low) A/D converter 90 PD17068 (3) P0A (P0A1, P0A0) I/O switching flag Output latch Write instruction VDD Port register (1 bit) Read instruction RES Signal (4) P0B3/HSCNT I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction Read instruction (The level is usually low. It is driven high only when a read instruction is executed.) Horizontal synchronizing signal counter 91 PD17068 (5) P1B3/TMIN I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction RES signal Basic timer (external clock) 10.2.2 mode. Using the I/O Port The I/O select register of control register P0A, P0B, P1B, P1C, or P2D sets the I/O port to input or output P0A, P0B, P1B, and P2D are bit I/O ports, each bit of which (each pin) can be set to input or output mode. To set the output data, write the data to the corresponding port register. To read the input data, execute an instruction to read the data. Section 10.2.3 describes the configurations of the I/O select registers of the ports. Sections 10.2.4 and 10.2.5 describe the use of the I/O port as an input port and/or output port. Section 10.2.6 provides notes on using the I/O port. 92 PD17068 10.2.3 Control Registers of the I/O Ports Port 0A bit I/O select register, port 0B bit I/O select register, port 1B bit I/O select register, port 1C group I/O select register, and port 2D bit I/O select register set pins P0A, P0B, P1B, P1C, and P2D in input or output mode, respectively. (1) to (5) below describe the configurations and functions of the control registers: (1) Port 0A bit I/O select register Flag symbol Register b3 P 0 A B I O 3 b2 P 0 A B I O 2 b1 P 0 A B I O 1 b0 P 0 A B I O 0 Address Read/write Port 0A bit I/O select register 37H R/W Sets the port to input or output mode. 0 1 Sets pin P0A0 to input mode. Sets pin P0A0 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0A1 to input mode. Sets pin P0A1 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0A2 to input mode. Sets pin P0A2 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0A3 to input mode. Sets pin P0A3 to output mode. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 93 PD17068 (2) Port 0B bit I/O select register Flag symbol Register b3 P 0 B B I O 3 b2 P 0 B B I O 2 b1 P 0 B B I O 1 b0 P 0 B B I O 0 Address Read/write Port 0B bit I/O select register 36H R/W Sets the port to input or output mode. 0 1 Sets pin P0B0 to input mode. Sets pin P0B0 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0B1 to input mode. Sets pin P0B1 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0B2 to input mode. Sets pin P0B2 to output mode. Sets the port to input or output mode. 0 1 Sets pin P0B3 to input mode. Sets pin P0B3 to output mode. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 94 PD17068 (3) Port 1B bit I/O select register Flag symbol Register b3 P 1 B B I O 3 b2 P 1 B B I O 2 b1 P 1 B B I O 1 b0 P 1 B B I O 0 Address Read/write Port 1B bit I/O select register 35H R/W Sets the port to input or output mode. 0 1 Sets pin P1B0 to input mode. Sets pin P1B0 to output mode. Sets the port to input or output mode. 0 1 Sets pin P1B1 to input mode. Sets pin P1B1 to output mode. Sets the port to input or output mode. 0 1 Sets pin P1B2 to input mode. Sets pin P1B2 to output mode. Sets the port to input or output mode. 0 1 Sets pin P1B3 to input mode. Sets pin P1B3 to output mode. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 95 PD17068 (4) Port 1C group I/O select register Flag symbol Register b3 b2 b1 b0 P 1 C G I O Address Read/write Port 1C group I/O select register 0 0 0 27H R/W Sets the port to input or output mode. 0 1 Sets pins P1C3 to P1C0 to input mode. Sets pins P1C3 to P1C0 to output mode. Always set to 0. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 96 PD17068 (5) Port 2D bit I/O select register Flag symbol Register b3 b2 P 2 D B I O 2 b1 P 2 D B I O 1 b0 P 2 D B I O 0 Address Read/write Port 2D bit I/O select register 0 26H R/W Sets the port to input or output mode. 0 1 Sets pin P2D0 to input mode. Sets pin P2D0 to output mode. Sets the port to input or output mode. 0 1 Sets pin P2D1 to input mode. Sets pin P2D1 to output mode. Sets the port to input or output mode. 0 1 Sets pin P2D2 to input mode. Sets pin P2D2 to output mode. Always set to 0. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 97 PD17068 10.2.4 Using an I/O Port as an Input Port Select the pin to be set to input mode, using the I/O select register of each port. The pins of port 1C can be set to input mode only in units of four bits. The specified input pin enters the floating (Hi-Z) status and waits for the input of an external signal. To read the input data, execute a read instruction (such as SKT) for the port register corresponding to the pin. If the signal input to the pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for the port register corresponding to an input port, the contents of the output latch are rewritten. 10.2.5 Using an I/O Port as an Output Port Select the pin to be set to output mode, using the I/O select register of each port. The pins of port 1C can be set in the output mode only in units of four bits. The specified output pin outputs the contents of the output latch. To set the output data, execute a write instruction (such as MOV) for the port register corresponding to the pin. To output a high signal to a pin, write 1. To output a low signal, write 0. To set a port to the floating state, set the port to input mode. If a read instruction (such as SKT) is executed for the port register corresponding to an output port, the contents of the output latch are read. For the P0A0 and P0A1 pins, the status of the pin is read as is. The contents of the output latch and the read data may differ (see Section 10.2.6). 10.2.6 Notes on Using the I/O Port If the P0A0 and P0A1 pins are used for output as described below, the contents of the output latches may be rewritten. Example Setting the P0A0 and P0A1 pins as output ports INITFLG NOT P0ABIO3, NOT P0ABIO2, P0ABIO1, P0ABIO0 ; Sets the P0A1 and P0A0 pins to output mode. INITFLG NOT P0A3, NOT P0A2, POA1, POA0 ; # P0A1 ; Outputs a high signal to the P0A1 and P0A0 pins. ; Outputs a low signal to the P0A1 pin. CLR1 AND Macro expansion . MF. P0A1 SHR 4, #. DF. (NOT P0A1 AND 0FH) If the signal on pin P0A0 is driven low by the execution of instruction the contents of the output latch of pin P0A0 to 0. # above, the CLR1 instruction rewrites If an instruction to read, the contents of port register P0A are executed when the P0A0 or P0A1 pin is set to output mode, the contents of the output latch are rewritten to the current signal level of the pin, even though the actual contents of the output latch are not changed. 98 PD17068 10.2.7 Statuses of the I/O Ports upon Reset (1) At power-on reset All pins are set to input mode. The contents of the output latches are set to 0. (2) At CE reset All pins are set to input mode. The contents of the output latches are retained. (3) At a clock-stop All pins are set to input mode. The contents of the output latches are retained. (4) In the halt state The previous statuses are retained. 10.3 10.3.1 GENERAL-PURPOSE INPUT PORT (P0D) Configuration of the Input Port The configuration of the input port is shown below: q P0D (P0D3 to P0D0) To the A/D converter VDD Write instruction Port register (1 bit) Input latch Read instruction Read instruction 10.3.2 Using the Input Port To read the input data, execute an instruction to read the contents of port register P0D (such as SKT). If the signal input to a pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for a port register, nothing changes. 99 PD17068 10.3.3 Notes on Using the Input Port P0D is internally pulled down if it is used as a general-purpose port. 10.3.4 Statuses of the Input Port upon Reset (1) At power-on reset All pins are set to input mode. (2) At CE reset All pins are set to input mode. (3) At a clock-stop All pins are set to input mode. They are internally pulled down. (4) In the halt state The previous statuses are retained. 10.4 10.4.1 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A, P1D, P2A, P2B, P2C) Configurations of the Output Ports The configurations of the output ports are shown in (1) and (2) below: (1) P0C (P0C3, P0C2, P0C1, P0C0), P1D (P1D3, P1D2, P1D1, P1D0) VDD Output latch Write instruction Port register (1 bit) Read instruction 100 PD17068 (2) P1A (P1A3, P1A2, P1A1, P1A0), P2A (P2A0), P2B (P2B3, P2B2, P2B1, P2B0), P2C (P2C3, P2C2, P2C1, P2C0) Output latch Write instruction Port register (1 bit) Read instruction 10.4.2 Using the Output Port The output port outputs the contents of the output latch from each pin. To set the output data, execute a write instruction (such as MOV) for the port register corresponding to each pin. To output a high signal to a pin, write 1. To output a low signal, write 0. The pins of P1A, P2A, P2B, and P2C are N-ch open-drain output. The pins enter the floating status if a high signal is output. If a read instruction (such as SKT) is executed for a port register, the contents of the output latch are read. 10.4.3 Statuses of the Output Port upon Reset (1) At power-on reset The contents of the output latch are output. The contents of the output latch are undefined. If required, initialize them by a program before setting a pin to output mode. (2) Upon CE reset The contents of the output latch are output. The output latch retains the data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (3) Upon a clock stop The contents of the output latch are output. The output latch retains the last data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (4) In the halt state The previous statuses are retained. 101 PD17068 11. INTERRUPT 11.1 OUTLINE OF THE INTERRUPT BLOCK Fig. 11.1 is an outline of the interrupt block. As shown in the figure, when an interrupt is requested by peripheral hardware, the interrupt block suspends the program currently being executed and causes a branch to a vector address. The interrupt block contains interrupt control blocks, provided for each item of peripheral hardware, and an interrupt enable flip-flop that enables all interrupts. The interrupt block also contains a stack pointer, an address stack register, a program counter, and an interrupt stack, all of which are controlled when an interrupt is accepted. The interrupt control block for each item of peripheral hardware consists of an interrupt request flag (IRQxxx) that detects an interrupt request, an interrupt enable flag (IPxxx) that enables the interrupt, and a vector address generator (VAG) that specifies a vector address when the interrupt is accepted. The following lists the peripheral hardware that supports the interrupt function: * INT0 pin * INTNC pin * Timer 0 * Timer 1 * Basic timer 2 * VRAM pointer * Interrupt group 0 (timer 0 overflow) * Interrupt group 1 (VSYNC or HSYNC signal) * Serial interface 0 * Serial interface 1 102 PD17068 Fig. 11-1 Schematic Diagram of Interrupt Block Interrupt control block IPGRP0 flag Interrupt group 0 IRQGRP0 flag Vector address generator 01H Program counter Stack pointer IPSIO1 flag Address stack register Serial interface 1 IRQSIO1 flag Vector address generator 02H System register IPSIO0 flag Serial interface 0 IRQSIO0 flag Vector address generator 03H Interrupt stack 1PGRP1 flag Interrupt group 1 1RQGRP1 flag Vector address generator 04H IPIDCVP flag VRAM pointer IRQIDCVP flag Vector address generator 05H IPBTM2 flag Basic timer 2 IRQBTM2 flag Vector address generator 06H IPTM1 flag Timer 1 IRQTM1 flag Vector address generator 07H IPTM0 flag Timer 0 IRQTM0 flag Vector address generator 08H IP0 flag INT0 pin IRQ0 flag Vector address generator 09H IPNC flag INTNC pin IRQNC flag Vector address generator 0AH DI, EI instructions Interrupt enable flip-flop 103 PD17068 11.2 INTERRUPT CONTROL BLOCKS An interrupt control block is provided for each item of peripheral hardware. The block indicates whether an interrupt has been requested by the associated peripheral hardware, enables the interrupt, and generates a vector address when the interrupt is accepted. 11.2.1 Formats and Functions of Interrupt Request Flags (IRQxxx) When an interrupt request is received from an item of peripheral hardware, the corresponding interrupt request flag is set to 1. It is reset to 0 once the interrupt has been accepted. When "1" is written into an interrupt request flag, via the window register, the effect is the same as when the corresponding interrupt request is generated. When interrupts are not enabled, for example, the interrupt request state can be detected by reading these interrupt request flags. Once an interrupt request flag has been set to 1, it is not reset until the corresponding interrupt request is accepted, or a "0" is written into the flag via the window register. When more than one interrupt request occurs at any one time, and one of these interrupt requests is accepted, the interrupt request flags for the other interrupt requests are not reset. The interrupt request flags are set in interrupt request registers in the register file. Figs. 11-2 to 11-11 illustrate the formats and functions of the interrupt request registers. Fig. 11-2 Format of Interrupt Request Register 1 Flag symbol Register b3 I N T N C b2 b1 b0 I R Q N C Address Read/write Interrupt request register 1 0 0 3FH R/W R for bit 3 only Sets the interrupt request state for the INTNC pin. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Detects the input level on the INTNC pin. 0 1 Low Level High Level Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 104 PD17068 Fig. 11-3 Format of Interrupt Request Register 2 Flag symbol Register b3 Interrupt request register 2 I N T 0 b2 b1 b0 I R Q 0 R/W R for bit 3 only Address Read/write 0 0 3EH Sets the interrupt request state for the INT0 pin. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Detects the input level on the INT0 pin. 0 1 Low level High level Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 Fig. 11-4 Format of Interrupt Request Register 3 Flag symbol Register b3 b2 b1 b0 I R Q T M 0 Address Read/write Interrupt request register 3 0 0 0 3DH R/W Sets the timer 0 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 105 PD17068 Fig. 11-5 Format of Interrupt Request Register 4 Flag symbol Register b3 b2 b1 b0 I R Q T M 1 Address Read/write Interrupt request register 4 0 0 0 3CH R/W Sets the timer 1 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Fig. 11-6 Format of Interrupt Request Register 5 Flag symbol Register b3 b2 b1 b0 I R Q B T M 2 Address Read/write Interrupt request register 5 0 0 0 3BH R/W Sets the basic timer 2 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 106 PD17068 Fig. 11-7 Format of Interrupt Request Register 6 Flag symbol Register b3 b2 b1 b0 I R Q I D C V P Address Read/write Interrupt request register 6 0 0 0 3AH R/W Sets the VRAM pointer interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Fig. 11-8 Format of Interrupt Request Register 7 Flag symbol Register b3 I N T G R P 1 b2 b1 b0 I R Q G R P 1 Address Read/write Interrupt request register 7 0 0 2CH R/W R for bit 3 only Sets the interrupt group 1 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Detects the input level of the VSYNC or HSYNC signal. 0 1 Low Level High Level Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 107 PD17068 Fig. 11-9 Format of Interrupt Request Register 8 Flag symbol Register b3 b2 b1 b0 I R Q S I O 0 Address Read/write Interrupt request register 8 0 0 0 2BH R/W Sets the serial interface 0 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Fig. 11-10 Format of Interrupt Request Register 9 Flag symbol Register b3 b2 b1 b0 I R Q S I O 1 Address Read/write Interrupt request register 9 0 0 0 2AH R/W Sets the serial interface 1 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 108 PD17068 Fig. 11-11 Format of Interrupt Request Register 10 Flag symbol Register b3 b2 b1 b0 I R Q G R P 0 Address Read/write Interrupt request register 10 0 0 0 29H R/W Sets the interrupt group 0 interrupt request state. 0 1 Interrupt not requested Interrupt requested Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 109 PD17068 11.2.2 Interrupt Enable Flags (IPxxx) The interrupt enable flags enable the interrupts requested from the corresponding peripheral hardware. An interrupt can be accepted only when all of the following conditions are satisfied: * The interrupt is enabled by the setting of the corresponding interrupt enable flag. * The corresponding interrupt request flag indicates that an interrupt request has occurred. * The EI instruction (enabling all interrupts) has been executed. The interrupt enable flags are arranged in interrupt enable registers on the register file. Figs. 11-12 to 11-14 show the formats and functions of the interrupt enable registers. Fig. 11-12 Format of Interrupt Enable Register 1 Flag symbol Register b3 I P T M 1 b2 I P T M 0 b1 I P 0 b0 I P N C Address Read/write Interrupt enable register 1 2FH R/W Specifies whether to enable interrupts for the INTNC pin. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for the INT0 pin. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for timer 0. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for timer 1. 0 1 Disables interrupts. Enables interrupts. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 110 PD17068 Fig. 11-13 Format of Interrupt Enable Register 2 Flag symbol Register b3 I P S I O 0 b2 I P G R P 1 b1 I P I D C V P b0 I P B T M 2 Address Read/write Interrupt enable register 2 2EH R/W Specifies whether to enable interrupts for basic timer 2. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for the VRAM pointer. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for interrupt group 1. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for serial interface 0. 0 1 Disables interrupts. Enables interrupts. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 111 PD17068 Fig. 11-14 Format of Interrupt Enable Register 3 Flag symbol Register b3 b2 b1 I P G R P 0 b0 I P S I O 1 Address Read/write Interrupt enable register 3 0 0 2DH R/W Specifies whether to enable interrupts for serial interface 1. 0 1 Disables interrupts. Enables interrupts. Specifies whether to enable interrupts for interrupt group 0. 0 1 Disables interrupts. Enables interrupts. Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 11.2.3 Vector Address Generator (VAG) When an interrupt requested from an item of peripheral hardware has been accepted, the vector address generator generates the branch address (vector address) of a program memory location for the accepted interrupt source. Table 11-1 lists the vector addresses generated for different interrupt sources. Table 11-1 Vector Addresses for Different Interrupt Sources Interrupt source INTNC pin INT0 pin Timer 0 Timer 1 Basic timer 2 VRAM pointer Interrupt group 1 (VSYNC or HSYNC pin) Serial interface 0 Serial interface 1 Interrupt group 0 (timer 0 overflow) Vector address 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 112 PD17068 11.3 11.3.1 INTERRUPT STACK REGISTER Format and Functions of the Interrupt Stack Register Fig. 11-15 shows the format of the interrupt stack register. When an interrupt is accepted, the contents of the following system registers are saved in the interrupt stack register: * Window register (WR) * Bank register (BANK) * General-purpose register pointer (RP) * Program status word (PSWORD) When an interrupt is accepted, the contents of the above system registers are saved in the interrupt stack register. Then, the contents of all system registers, except the window register, are reset to 0. Up to two levels of the system register contents can be saved in the interrupt stack register. Therefore, up to two levels of interrupt are possible. The contents of the system registers are restored from the interrupt stack register once the interrupt return instruction (RETI instruction) has been executed. Fig. 11-15 Format of the Interrupt Stack Register Interrupt stack register (INTSK) Window stack (WRSK) Bank stack (BANKSK) Register pointer stack, high (RPHSK) b0 b3 - - b2 - - b1 b0 Register pointer stack, low (RPLSK) b3 b2 b1 b0 b3 Status stack (PSWSK) Name Bit 0H 1H b3 b2 b1 b0 b3 - - b2 - - b1 b2 b1 b0 Remark 11.3.2 - : Bit not saved Interrupt Stack Operation Fig. 11-16 illustrates the operation of the interrupt stack. If more than two interrupt levels are accepted, the data saved first is removed from the stack, and so must be saved by software. 113 PD17068 Fig. 11-16 Interrupt Stack Operation (a) When the number of interrupt levels does not exceed 2 Not defined Not defined When VDD on A Not defined Interrupt B B A RETI A Not defined RETI Not defined Not defined Interrupt A (b) When the number of interrupt levels exceeds 2 A Not defined Interrupt A Interrupt B B A Interrupt C C B Interrupt D D C Interrupt E E D RETI D D RETI D D 11.4 STACK POINTER, ADDRESS STACK REGISTER, AND PROGRAM COUNTER The address stack register holds the return address to which control returns from an interrupt handling routine. The stack pointer specifies the address of the address stack register. When an interrupt is accepted, the value of the stack pointer is decremented by one, and the current value of the program counter is saved in the address stack register location specified by the stack pointer. When the interrupt return instruction (RETI instruction) is executed after execution of the interrupt handling routine, the contents of the address stack register location, specified by the stack pointer, are restored to the program counter. The stack pointer is then incremented by one. See also Chapter 3. 11.5 INTERRUPT ENABLE FLIP-FLOP (INTE) The interrupt enable flip-flop enables all interrupts. When this flip-flop is set, all interrupts are enabled. If the flip-flop is reset, all interrupts are disabled. The flip-flop is set and reset by using dedicated instructions: The EI instruction (for setting) and the DI instruction (for resetting). The EI instruction causes the flip-flop to be set once the instruction immediately after the EI instruction has been executed. The DI instruction resets the flip-flop upon execution of the DI instruction. When an interrupt is accepted, the flip-flop is reset automatically. Nothing occurs when a DI instruction is executed while interrupts are disabled (DI state), or when an EI instruction is executed while interrupts are enabled (EI state). When a power-on reset occurs, when a clock-stop instruction is executed, or when a CE reset occurs, the flip-flop is reset. 114 PD17068 11.6 11.6.1 ACCEPTING INTERRUPTS Operation for Accepting Interrupts and Priorities Interrupts are accepted in the following sequence: (1) When an interrupt condition (for example, a high-to-low input signal transition occurs on the INT0 pin) is satisfied, the peripheral hardware outputs an interrupt request signal to the associated interrupt request block. (2) Upon receiving of the interrupt request signal from the peripheral hardware, the interrupt request block sets its interrupt request flag (IRQ0 flag for the INT0 pin, for example) to 1. (3) If the corresponding interrupt enable flag (IP0 flag for the IRQ0 flag, for example) is set to 1 when the interrupt request flag has been set to 1, the interrupt request block outputs 1. (4) The signal output from the interrupt request block is ANDed with the output of the interrupt enable flip-flop, and the interrupt acceptance signal is output. The interrupt enable flip-flop is set to 1 with the EI instruction, and is reset to 0 with the DI instruction. If 1 is output from an interrupt request block while the interrupt enable flip-flop is set to 1, an interrupt is accepted. When an interrupt is accepted, the output of the interrupt enable flip-flop is applied to each interrupt request block via an AND circuit, as shown in Fig. 11-1. The signal applied to the interrupt request block for the accepted interrupt resets the corresponding interrupt request flag to 0, and causes the vector address corresponding to the interrupt to be output. If an interrupt request block outputs 1 at this time, the interrupt acceptance signal is not transferred to the subsequent interrupt request blocks. When more than one interrupt request is generated at any one time, the interrupts are accepted according to the priorities shown below. If the interrupt enable flag for an interrupt source is not set to 1, the interrupt for that interrupt source is not accepted. Therefore, an interrupt with a high hardware priority can be disabled by resetting the corresponding interrupt enable flag to 0. Table 11-2 Interrupt Priorities Interrupt source INTNC pin INT0 pin Timer 0 Timer 1 Basic timer 2 VRAM pointer Interrupt group 1 Serial interface 0 Serial interface 1 Interrupt group 0 Priority 1 2 3 4 5 6 7 8 9 10 115 PD17068 11.6.2 Timing Charts for Accepting Interrupts Fig. 11-17 shows the timing charts for accepting interrupts. The timing charts in (1) of Fig. 11-17 apply to the use of one interrupt. Timing chart (a) in (1) shows how an interrupt is accepted when the interrupt request flag is set to 1. Timing chart (b) in (1) shows how an interrupt is accepted when the interrupt enable flag is set to 1. In both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and interrupt enable flag have all been set to 1. If the last flag or flip-flop is set to 1 during the execution of MOVT DBF, the first instruction cycle of the @AR instruction, or an instruction that satisfies the skip conditions, the interrupt is accepted after the execution of MOVT DBF, the second cycle of the @AR instruction, or the skipped instruction (NOP instruction). The interrupt enable flip-flop is set in the instruction cycle immediately after the EI instruction. This means that when the interrupt request flag is set during the execution cycle of the EI instruction, the instruction immediately after the EI instruction is executed, after which the interrupt is accepted. The timing charts in (2) of Fig. 11-17 apply to the use of multiple interrupts. When multiple interrupts are used, and their interrupt enable flags are all set, they are accepted according to the hardware priorities. The hardware priorities, however, can be changed by programming the settings of the interrupt enable flags. The interrupt cycle shown in Fig. 11-17 is applied to operations performed after an interrupt has been accepted; these operations include the resetting of the interrupt request flag, specification of a vector address, and saving of the program counter contents. This cycle requires 2 s (when an 8-MHz crystal is used), which is equal to the time required for executing one instruction. For details, see Section 11.7. 116 PD17068 Fig. 11-17 Timing Charts for Accepting Interrupts (1/2) (1) When one interrupt type (example: Low-to-high transition on the INT0 pin) is used (a) With no interrupt mask time set with interrupt enable flag (IPxxx) # When an interrupt is accepted while a normal instruction is being executed (the instruction is not a MOVT instruction or an instruction that satisfies the skip conditions) MOV POKE WR, #0001B INTPM1, WR Normal instruction Interrupt cycle Instruction EI INTE INT0 pin IRQ0 flag IP0 flag 1 instruction cycle 2 s Interrupt enable period Interrupt handling routine $ When an interrupt is accepted while a MOVT instruction or an instruction that satisfies the skip conditions is being executed MOV POKE WR, #0001B INTPM1, WR MOVT DBF, @AR skip instruction Interrupt accepted Instruction EI Interrupt cycle INTE INT0 pin IRQ0 flag IP0 flag Interrupt enable period Interrupt handling routine Interrupt accepted (b) With an interrupt pending period set with the interrupt enable flag Instruction INTE INT0 pin IRQ0 flag IP0 flag EI MOV POKE WR, #0001B INTPM1, WR Interrupt cycle Interrupt pending period Interrupt handling routine Interrupt accepted 117 PD17068 Fig. 11-17 Timing Charts for Accepting Interrupts (2/2) (2) When multiple interrupts (example: INT0 and INTNC pins) are used (a) With hardware priority Instruction MOV#0011B POKE WR WR, INTPM1, INTE INTNC pin IRQNC flag INT0 pin IRQ0 flag IP0 flag IPNC flag Interrupt pending period INTNC pin interrupt handling INT0 pin interrupt pending period Interrupt cycle Interrupt cycle EI EI INT0 pin interrupt handling INTNC pin interrupt accepted INT0 pin interrupt accepted (b) With software priority Instruction MOV#0010B POKE WR INTPM1, WR, INTE INTNC pin IRQNC flag INT0 pin IRQ0 flag IPNC flag IP0 flag INTNC pin interrupt pending period Interrupt pending period INT0 pin interrupt handling INTNC pin interrupt handling Interrupt cycle POKE MOV WR, #0011B INTPM1, WR EI EI Interrupt cycle INT0 pin interrupt accepted INTNC pin interrupt accepted 118 PD17068 11.7 OPERATION AFTER AN INTERRUPT IS ACCEPTED When an interrupt is accepted, the following operations are performed, automatically and in the order shown: (1) The interrupt enable flip-flop and the interrupt request flag for the accepted interrupt request are reset to 0. This indicates that the interrupt disable state is entered. (2) The value in the stack pointer is decremented by one. (3) The program counter contents are saved to the address stack register location specified by the stack pointer. The saved program counter contents indicate the program memory address subsequent to the address at which the interrupt was accepted. If the interrupt was accepted during the execution of a branch instruction, for example, the branch destination address is indicated in the program counter. If the interrupt was accepted during the execution of a subroutine call instruction, the called address is indicated. If the skip conditions are satisfied in a skip instruction, the next instruction is executed as an NOP instruction, after which the interrupt is accepted. In this case, the program counter indicates the address subsequent to the skipped instruction. (4) The contents of the window register (WR), bank register (BANK), general-purpose register pointer (RP), and program status word (PSWORD) are saved to the interrupt stack. (5) The contents of the vector address generator for the accepted interrupt are transferred to the program counter to branch to the interrupt handling routine. For operations (1) to (5) above, a special one-instruction cycle (2 s), that does not involve the execution of a normal instruction, is required. Such an instruction cycle is called an interrupt cycle. This means that one instruction cycle (2 s) is required to branch to the corresponding vector address after the interrupt has been accepted. 11.8 RETURN FROM THE INTERRUPT HANDLING ROUTINE To return control from the interrupt handling routine to the processing being performed when the interrupt was accepted, the interrupt return instruction (RETI instruction) is used. When the RETI instruction is executed, the following operations are performed, automatically and in the order shown: (1) The contents of the address stack register location, specified by the stack pointer, are restored to the program counter. (2) The interrupt stack contents are restored to the window register (WR), bank register (BANK), generalpurpose register pointer (RP), and program status word (PSWORD). (3) The stack pointer value is incremented by one. Operations (1) to (3) above are performed during the one instruction cycle (2 s) in which the RETI instruction is executed. The RETI instruction differs from the RET and RETSK instructions, which are subroutine return instructions, only in operation (2) above (system register restoration). 119 PD17068 11.9 11.9.1 EXTERNAL INTERRUPTS (INT0 PIN, INTNC PIN, VSYNC PIN, HSYNC PIN) Outline of External Interrupts Fig. 11-18 is an outline of the external interrupts. As shown in the figure, an external interrupt request occurs on a rising or falling edge of a signal applied to the INT0 pin, INTNC pin, VSYNC pin, or HSYNC pin. Whether the rising or falling edge is to be used for requesting interrupts can be programmed separately for each pin. The INTNC pin can be used as a special input pin for remote control by selecting an appropriate pulse width for accepting an interrupt. Each pin is a Schmitt-triggered input. This can prevent malfunctions due to noise. Pulse widths of less than 1 s are ignored. As the interrupt source, either the VSYNC or HSYNC pin (interrupt group 1) can be specified with the IGRP1SL flag. See Section 11.10.7. Fig. 11-18 Schematic Diagram of External Interrupts Interrupt control block INT0 flag IEG0 flag INT0 pin Schmitt-triggered INTNC flag Edge detection block IRQ0 flag INTNCMD0 INTNCMD2 flags IEGNC flag INTNC pin Schmitt-triggered INTGRP1 flag Edge detection block IRQNC flag VSYNC pin Schmitt-triggered IEGGRP1 flag Selection circuit Edge detection block IRQGRP1 flag HSYNC pin IGRP1SL flag Schmitt-triggered Remark INT0 INTNC INTGRP1 IEG0 IEGNC IEGGRP1 IGRP1SL INTNCMD0 to INTNCMD2 : Selects the interrupt source for interrupt group 1. : Select the pulse width for accepting interrupts. Select the interrupt edge. Detect pin states. 120 PD17068 11.9.2 Edge Detection Blocks The edge detection blocks detect the input signal edge (rising or falling edge) that causes an interrupt request to be generated for the INT0 pin, INTNC pin, and VSYNC and HSYNC pins. Each input signal edge is selected with the interrupt edge selection register. Fig. 11-19 shows the format and functions of the interrupt edge selection register. Fig. 11-19 Format of the Interrupt Edge Selection Register Flag symbol Register b3 b2 I E G G R P 1 b1 I E G 0 b0 I E G N C Address Read/write Interrupt edge selection register 0 1FH R/W Specifies the input edge at which an interrupt request is generated. (INTNC pin) 0 1 Rising edge Falling edge Specifies the input edge at which an interrupt request is generated. (INT0 pin) 0 1 Rising edge Falling edge Specifies the input edge at which an interrupt request is generated. (HSYNC or VSYNC pin: Selected by the IGRP1SL flag) 0 1 Rising edge Falling edge Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 Note that when the edge used for requesting interrupts is changed by changing the setting of the interrupt edge selection flag, an interrupt request signal may be issued immediately. Suppose that the IEG0 flag is set to 1 (falling edge), and that a high is applied to the INT0 pin, as shown in Table 11-3. Here, note that if the IEG0 flag is reset to 0, the edge detection circuit assumes that a rising edge has been input, and generates an interrupt request. 121 PD17068 Table 11-3 Interrupt Requests Generated by Changing the IEG0, IEGNC, and IEGGRP1 Flag Settings Change in interrupt edge selection flag setting 1 (Falling edge) 0 (Rising edge) 0 (Rising edge) 1 Pin state Generation of interrupt request Interrupt request flag state Low High Low High Not generated Generated Generated Not generated Previous state is held. Set to 1. Set to 1. Previous state is held. (Falling edge) 11.9.3 Interrupt Control Block The levels of the signals applied to the pins can be detected with the INTNC, INT0, and INTGRP1 flags, respectively. These flags are set and reset regardless of the interrupts. When the interrupt function is not being used, these flags can be used as a 3-bit general-purpose input port. When interrupts are not enabled, these flags can be used as general-purpose ports that can detect a rising or falling edge by reading the interrupt request flags. In this case, the interrupt request flags are not reset automatically; they must be reset by the program. Also see Section 11.2.1. 122 PD17068 11.9.4 Input Pin for Remote Control (INTNC) The input pin for remote control (INTNC pin) differs from normal external interrupt input pins in that the pulse width for accepting interrupts can be selected from among several width options. The pulse width is specified with the INTNC mode select register. Fig. 11-20 shows the format and functions of the INTNC mode select register. Fig. 11-20 Format of the INTNC Mode Select Register Flag symbol Register b3 b2 I N T N C M D 2 b1 I N T N C M D 1 b0 I N T N C M D 0 Address Read/write INTNC mode selector register 0 15H R/W Specifies the pulse width for accepting INTNC pin interrupts. 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Accepts interrupts on the pulse edge. 200 s 400 s 2 ms 4 ms Not to be set Other than above Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 11.10 INTERNAL INTERRUPTS The following seven internal interrupt types are provided. * Timer 0 * Timer 1 * Basic timer 2 * VRAM pointer * Serial interface 0 * Serial interface 1 * Interrupt group 0 (timer 0 overflow) 123 PD17068 11.10.1 Timer 0 Interrupt An interrupt request is generated at regular intervals. See Chapter 12 for details. 11.10.2 Timer 1 Interrupt An interrupt request is generated at regular intervals. See Chapter 12 for details. 11.10.3 Basic Timer 2 Interrupt An interrupt request is generated at regular intervals. See Chapter 12 for details. 11.10.4 VRAM Pointer Interrupt An interrupt request is generated at regular intervals. See Chapter 16 for details. 11.10.5 Serial Interface 0 Interrupt Upon the completion of serial output or serial input, an interrupt request can be generated. See Chapter 15 for details. 11.10.6 Serial Interface 1 Interrupt An interrupt request can be generated on the rising edge of the eighth clock pulse, counting from the start of serial interface 1. See Chapter 15 for details. 124 PD17068 11.10.7 Interrupts by Interrupt Group 0 and Interrupt Group Selection Register Interrupt group 0 generates an interrupt request when timer 0 overflows. For details of the conditions governing the request of interrupts, see Chapter 12. Whether to use interrupts caused by the overflow of timer 0 is specified with the IGRP0SL flag of the interrupt group selection register. In addition, the interrupt group selection register selects the interrupt source for interrupt group 1 (external interrupts). Fig. 11-21 shows the format and functions of the interrupt group selection register. Caution To use interrupts caused by the overflow of timer 0, both the interrupt enable flag (IPGRP0) and the IGRP0SL flag of the interrupt group selection register must be set to 1. Fig. 11-21 Format of the Interrupt Group Selection Register Flag symbol Register b3 b2 b1 I G R P 1 S L b0 I G R P 0 S L Address Read/write Interrupt group selection register 0 0 0FH R/W Specifies whether to use timer 0 overflow interrupts (group 0). 0 1 Does not use interrupts. Uses interrupts. Selects the interrupt source (group 1). 0 1 VSYNC signal HSYNC signal Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 125 PD17068 12. TIMERS The timers in the PD17068 are used to manage the time required to execute programs. 12.1 OVERVIEW Fig. 12-1 shows the block diagrams of the timers. The PD17068 contains the following six different timers. * Basic timer 0 * Basic timer 1 * Basic timer 2 * Timer 0 (modulo scheme) * Timer 1 (modulo scheme) * Clock timer Basic timers 0 and 1 are realized by detecting the state of a flip-flops that is set at constant intervals, using software. Basic timer 2 issues an interrupt request at constant intervals. Timers 0 and 1 are modulo timers. They issue an interrupt request at constant intervals. The clock timer counts seconds, minutes, hours, and days. Basic timer 0 is used also to detect a power failure. The clock pulses for the timers except the clock timer are generated by dividing the frequency of the system clock (8 MHz). The clock pulse for the clock timer is generated by dividing a frequency of 32 kHz. Fig. 12-1 Overview of Timers (1/2) (1) Basic timer 0 8 MHz Clock selection block Flip-flop BTM0CY flag (2) Basic timer 1 8 MHz External clock Clock selection block Flip-flop BTM1CY flag (3) Basic timer 2 8 MHz External clock Clock selection block Interrupt request 126 PD17068 Fig. 12-1 Overview of Timers (2/2) (4) Timer 0 8 MHz Clock selection block Start/stop 12-bit counter Interrupt request Match detected Interrupt request Modulo register (5) Timer 1 8 MHz Clock selection block Start/stop 8-bit counter Match detected Interrupt request Modulo register (6) Clock timer Frequency divider Seconds counter Minutes counter Hours counter Days counter Reset control 32 kHz 127 PD17068 12.2 12.2.1 BASIC TIMER 0 Overview of Basic Timer 0 Fig. 12-2 shows the block diagram of basic timer 0. Basic timer 0 is realized by detecting the state of a flip-flop that is set at constant intervals, using the BTM0CY flag (bit 0 at address RF:17H). The contents of the flip-flop correspond to the states of the BTM0CY flag on a one-to-one basis. When the BTM0CY flag is read-accessed for the first time after a power-on reset, it is read as "0". From then on, the flag is set to "1" at constant intervals. After the CE pin goes from a low level to a high level, a CE reset occurs simultaneously when the BTM0CY flag is set next time. A power failure can therefore be detected by reading the BTM0CY flag when a system reset (power-on or CE reset) occurs. See Chapter 20 for power failure detection. Fig. 12-2 Block Diagram of Basic Timer 0 Clock selection block BTM0CK0 flag BTM0CK1 flag Set/clear 8 MHz Frequency divider Selector Flip-flop BTM0CY flag Remarks 1. BTM0CK1 and BTM0CK0 (bits 1 and 0 of the basic timer 0 clock select register, respectively; see Fig. 12-3) specify the time interval at which the BTM0CY flag is set. 2. BTM0CY (bit 0 of the basic timer 0 carry flip-flop judge register; see Fig. 12-4) reflects the state of the flip-flop. 12.2.2 Clock Selection Block The clock selection block divides the frequency of the system clock (8 MHz) and specifies the time interval at which the BTM0CY flag is set, using the basic timer 0 clock select register. Fig. 12-3 shows the configuration and function of the basic timer 0 clock select register. 128 PD17068 Fig. 12-3 Configuration of the Basic Timer 0 Clock Select Register Flag symbol Register b3 b2 b1 B T M 0 C K 1 b0 B T M 0 C K 0 Address Read/write Basic timer 0 clock select register 0 0 0CH R/W Specify the time interval at which the BTM0CY flag is set. 0 0 1 1 0 1 0 1 100 ms 5 ms 1 ms 1 ms Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Hold 12.2.3 Flip-Flop and BTM0CY Flag The flip-flop is set at constant intervals, and its state is detected using the BTM0CY flag of the basic timer 0 carry flip-flop judge register. The BTM0CY flag is reset to "0" by reading its contents into a window register using the PEEK instruction (Read & Reset). The BTM0CY flag is "0" at a power-on reset. It becomes "1" at a CE reset. So, it can be used as a power failure detection flag. Even when power is supplied, the BTM0CY flag will not be set until a read instruction is executed. Once a read instruction is executed, the flag is set at constant intervals. Fig. 12-4 shows the configuration and function of the basic timer 0 carry flip-flop judge register. 129 PD17068 Fig. 12-4 Configuration of the Basic Timer 0 Carry Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 B T M 0 C Y Address Read/write Basic timer 0 0 carry flip-flop judge register 0 0 17H R & Reset Detects the state of the flip-flop. 0 1 The flip-flop is not set. The flip-flop is set. Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 1 1 12.2.4 Example of Using Basic Timer 0 A sample program follows. The following program performs process A at every one second. Example CLR2 LOOP: SKT1 BR ADD BR MOV BTM0CY NEXT M1, #1 NEXT M1, #0 ; Adds 1 to M1. ; Performs process A if M1 is 10 or greater (1 second). ; Branches to NEXT if BTM0CY is "0". BTM0CK1, BTM0CK0 ; Specifies that the BTM0CY flag be set at intervals of 100 ms. SKGE M1, #0AH Process A NEXT: Process B BR LOOP ; Performs process B and branches to LOOP. 130 PD17068 12.2.5 Time Interval Error in Basic Timer 0 There are two types of errors in basic timer 0; one type is related to the time interval at which the BTM0CY flag is detected, and the other type can occur when the time interval at which the BTM0CY flag is set is changed. Each type of error is described under (1) and (2). (1) Error related to the detection time of the BTM0CY flag The time interval at which the BTM0CY flag is detected must be shorter than the time interval at which the BTM0CY flag is set. (See Section 12.2.6.) In other words, assuming that the BTM0CY flag is detected at intervals of tCHECK and is set at intervals of tSET (100, 5, or 1 ms), the relationship between tCHECK and tSET must be as follows: tCHECK < tSET Under this condition, the time interval error encountered when the BTM0CY flag is detected is as follows: 0 < error < tSET Fig. 12-5 Basic Timer 0 Error Related to the Detection Time of the BTM0CY Flag H BTM0CY flag set pulse L tSET 1 BTM0CY flag 0 tCHECK1 SKT1 BTM0CY tCHECK2 SKT1 BTM0CY tCHECK3 SKT1 BTM0CY SKT1 BTM0CY # "1". When the flag is detected at $ % & As shown in Fig. 12-5, when the BTM0CY flag is detected at &. %, because it is "0", the timer is not updated until it is detected again at $, the timer is updated because the flag is Therefore, the timer is incremented by tCHECK3. 131 PD17068 (2) Error due to a change to the time interval at which the BTM0CY flag is set The BTM0CK1 and BTM0CK0 flags specify the time interval at which the BTM0CY flag is set. As shown in Section 12.2.2, the time interval set pulse can be selected from three types, 1 kHz, 200 Hz, and 10 Hz. These three pulses operate independently. When the time interval set pulse is switched using the BTM0CK1 and BTM0CK0 flags, therefore, an error occurs as explained in the following example. Example ; # Process A INITFLG NOT BTM0CK1, BTM0CK0 ; Selects 200 Hz (5 ms) as the BTM0CY flag set pulse. ; $ Process A INITFLG BTM0CK1, NOT BTM0CK0 ; Selects 1 kHz (1 ms) as the BTM0CY flag set pulse. ; % INITFLG NOT BTM0CK1, BTM0CK0 ; Selects 200 Hz (5 ms) as the BTM0CY flag set pulse. With this coding, the BTM0CY flag set pulse is switched as shown in Fig. 12-6. Fig. 12-6 BTM0CY Flag Set Pulse Switching H 200 Hz internal pulse L H 1 kHz internal pulse L H BTM0CY flag set pulse L 1 BTM0CY flag 0 # $ % SKT1 BTM0CY As shown in Fig. 12-6, when the BTM0CY flag set time interval is switched, if the selected pulse falls, the BTM0CY flag maintains its previous state ($ in the figure). If the selected pulse rises, the BTM0CY flag is set to "1" (% in the figure). This example illustrates switching between 200 Hz (5 ms) and 1 kHz (1 ms). This explanation also applies to switching between 200 Hz and 10 Hz (100 ms) and between 1 kHz and 10 Hz. 132 PD17068 Consequently, if the BTM0CY flag set time interval is switched as shown in Fig. 12-7, a time interval error observed before the BTM0CY flag is set for the first time is as given below. - tSET < error < tCHECK tSET tCHECK : Newly selected BTM0CY flag set time interval : BTM0CY flag detection time interval The 10 Hz, 200 Hz, and 1 kHz internal pulses have a phase difference from one another. These phase differences are shorter than the pulse interval and included in the error described above. See Section 12.4.5 for each pulse phase difference. Fig. 12-7 Timer Error That Occurs When the BTM0CY Flag Set Time Interval Is Switched from A to B H Internal pulse A L H Internal pulse B L tSET H BTM0CY flag set pulse L H BTM0CY flag L SKT1 BTM0CY True timer interval Actual timer interval Time interval switched Actual timer interval True timer interval Time interval switched If the timer interval is switched right after the BTM0CY flag is detected, the BTM0CY flag is kept to be reset for one cycle, resulting in an error of tCHECK. 0 0 tCHECK tSET If the BTM0CY flag is detected right after the timer interval is switched, the flag appears to be "1", resulting in an error of -tSET. 133 PD17068 12.2.6 Cautions for Using Basic Timer 0 (1) BTM0CY flag detection time interval Keep the BTM0CY flag detection time interval shorter than the BTM0CY flag set time interval. Otherwise, the BTM0CY flag cannot be set if the time required for process B is longer than the BTM0CY flag set time interval, as shown in Fig. 12-8. Fig. 12-8 BTM0CY Flag and Its Detection H L 1 BTM0CY flag 0 BTM0CY flag set pulse # $ % & ( SKT1 BTM0CY SKT1 BTM0CY SKT1 BTM0CY Process A Process B Because the time required for process B is long after the BTM0CY flag, which is set to "1" at is detected, the BTM0CY flag, which is set to "1" at cannot be detected. $, %, (2) Sum of the timer update process time and the BTM0CY flag detection time interval As explained in (1), the BTM0CY flag detection time interval (tSET) must be kept shorter than the BTM0CY flag set time interval. Even when the BTM0CY flag detection time interval is short, however, if the timer update process time is long, a CE reset may prevent a normal timer update process. The following conditions must therefore be satisfied. tCHECK + tTIMER < tSET where tCHECK : BTM0CY flag detection time interval tTIMER : Timer update process time tSET : BTM0CY flag set time interval The coding that meets these conditions is given below. 134 PD17068 Example Timer update process and BTM0CY flag detection time interval START: CLR2 BTIMER: ; BTM0CK1, BTM0CK0 ; Specifies 100 ms as the BTM0CY flag set time ; interval. # BTM0CY AAA ; Updates the timer if the BTM0CY flag is "1". Timer update SKT1 BR BR AAA: BTIMER Process A BR BTIMER The timing chart for this coding is as follows: H CE pin L H BTM0CY flag set pulse L 1 BTM0CY flag 0 BTM0CY detection time interval tCHCK Timer update process tTIMER A CE reset occurs if this timer update process takes long time. # SKT1 BTM0CY # SKT1 BTM0CY CE reset 135 PD17068 (3) Correcting the basic timer 0 carry at a CE reset The following paragraphs describe an example of correcting the timer at a CE reset. As explained in the example, it is necessary to correct the timer at a CE reset, if the BTM0CY flag is used both to detect a power failure and to control the clock timer. The BTM0CY flag is reset (0) when the supply voltage is first applied (at a power-on reset), and kept disabled from being set until it is read-accessed using the PEEK instruction. When the CE pin goes from a low level to a high level, a CE reset occurs in synchronization with the rising edge of the BTM0CY flag set pulse, setting the BTM0CY flag to "1" and making it active. Detecting the state of the BTM0CY flag at a system reset (power-on or CE reset) can therefore check for a power failure. If the flag is "0", it means that a power-on reset has occurred. If it is "1", it means that a CE reset has occurred (power failure detection). In this case, a clock timer must keep operating even at a CE reset. However, reading the BTM0CY flag for power failure detection resets the flag (0) and makes it impossible to detect the set (1) state of the flag for one cycle. To solve this problem, it is necessary to update the clock timer if an attempt to detect a power failure detects a CE reset. See Section 20.6 for power failure detection. Example Correcting the timer at a CE reset (when the BTM0CY flag is used for both power failure detection and timer update) START : ; Program address 0000H ; # Process A BTM0CY INITIAL ; Built-in macro ; Checks the BTM0CY flag and branches to INITIAL ; if the flag is "0" (power failure detected). SKT1 BR BACKUP : ; $ Timer update by 100 ms ; Timer correction because of backup (CE reset) LOOP: ; % Process B SKF1 BR BR ; While performing process B, BTM0CY ;tests the BTM0CY flag and updates the timer. BACKUP LOOP BTM0CK1, BTM0CK0 ; Built-in macro ; The BTM0CY flag set time interval is set to ; 100 ms and process C is performed because a ; power failure (power-on reset) has occurred. Process C BR LOOP INITIAL : CLR2 Fig. 12-9 shows the timing chart for the above program. 136 PD17068 Fig. 12-9 Timing Chart 5V 0V H L H L H L 1 0 A C B B B B B B B BB B A B B B VDD CE 10 Hz internal pulse BTM0CY flag set pulse BTM0CY flag Program processing Program instruction #%%% Start at address 0 on a power-on reset Timer incremented % %% Timer incremented %% Timer incremented %% Timer incremented Start at address 0 on a CE reset # %% Timer incremented Timer updated because the BTM0CY flag has been detected to be set (1) Supply voltage applied BTM0CY flag detected Point A Point B Point C Point D Point E As shown in Fig. 12-9, when supply voltage VDD is applied, the 10 Hz internal pulse rises to make the program start at address 0000H. When the BTM0CY flag is detected at point A, the BTM0CY flag appears to be reset (0) because it is just after power is supplied. Consequently, it is determined that a power failure (power-on reset) has occurred. So, process C is performed to select 100 ms as the BTM0CY flag set pulse. Because the BTM0CY flag is once read-accessed at point A, the BTM0CY flag will be set (1) at intervals of 100 ms. Even when the CE pin goes to a low at point B and goes to a high at point C, the program continues to update the clock while performing process B, unless the clock stop instruction is executed. Because the CE pin goes from a low to a high at point C, a CE reset occurs at point D, where the BTM0CY flag set pulse rises, to start the program at address 0000H. When the BTM0CY flag is detected at point E, it is determined that a backup (CE reset) has occurred, because the flag appears to be set (1). Also, as easily seen from the figure, if the clock is not updated by 100 ms at point E, the clock loses 100 ms every time a CE reset occurs. If process A takes more than 100 ms to detect for a power failure at point E, it is impossible to detect the BTM0CY flag for two cycles. Therefore, process A must be performed within 100 ms. The above description applies also when either 5 ms or 1 ms is selected as the BTM0CY flag set pulse. It is necessary, therefore, to detect the BTM0CY flag for power failure detection after the program starts at address 0000H and before the BTM0CY flag is set. 137 PD17068 (4) When the BTM0CY flag is detected simultaneously with a CE reset As described in (3), a CE reset occurs at the same time the BTM0CY flag is set (1). Under this condition, if a read instruction is executed for the BTM0CY flag simultaneously with a CE reset, the read instruction takes preference. Therefore, if a BTM0CY flag read instruction occurs simultaneously with the rising edge of the BTM0CY flag set pulse that occurs after the CE pin goes from a low to a high, a CE reset occurs when the BTM0CY flag is set on the next cycle. This operation is illustrated in Fig. 12-10. Fig. 12-10 Operation That Occurs If a CE Reset Occurs Simultaneously with a BTM0CY Flag Read Instruction H L BTM0CY flag H set pulse L 1 BTM0CY flag 0 CE pin SKT 1 BTM0CY H BTM0CY flag set pulse L 1 BTM0CY flag 0 Instruction SKT1 BTM0CY (PEEK...) (SKT...) SKT 1 BTM0CY CE reset Built-in macro PEEK WR,. MF. BTM0CY SHR 4 2 s SKT WR, #, DF. BTM0CY AND 000FH If the BTM0CY flag is read during this period, a CE reset is deferred by one cycle. Normally, the program starts at address 0000H at this point, but a CE reset does occur because the program to read the BTM0CY flag also happens to run. Therefore, if a program is designed to detect the BTM0CY flag cyclically and has the BTM0CY flag detection time interval that matches the BTM0CY flag set time interval, a CE reset may not occur for ever. Observe the following cautions. Because one instruction cycle is 2 s (1/500 kHz), the BTM0CY flag is read at every 1 ms (2 s x 500) if the program is designed to detect the BTM0CY flag once every 500 instructions. In this case, regardless of which of 1, 5, and 100 ms is selected as the timer interval set pulse, a CE reset will not occur for ever once the BTM0CY flag set and detection time intervals coincide with each other. To solve this problem, do not create a program with a cycle that meets the following condition. (tSET x 500) X = n (where n is a natural number) tSET : BTM0CY flag set time interval X : Number of steps in a cycle that a BTM0CY flag read instruction is issued An example of a program that meets the above condition is given below. Do not create such a program. 138 PD17068 Example Process A SET2 BTM0CK1, BTM0CK0 ; Built-in macro ; Specifies 1 ms as the BTM0CY flag set pulse. LOOP : ; # SKT1 BR BTM0CY BBB ; Built-in macro AAA : 496 steps BR BBB : 496 steps BR LOOP LOOP In this example, a CE reset will not occur for ever if the BTM0CY flag happens to be set at a timing of a BTM0CY flag read instruction at #, because the read instruction is repeated at every 500 instructions. 139 PD17068 12.3 12.3.1 BASIC TIMER 1 Overview of Basic Timer 1 Fig. 12-11 shows the block diagram of basic timer 1. Basic timer 1 is realized by detecting the state of a flip-flop that is set at constant intervals, using the BTM1CY flag (bit 0 at address RF:16H). The contents of the flip-flop corresponds the states of the BTM1CY flag on a one-to-one basis. Basic timer 1 can use an external clock input at the P1B3/TMIN pin as its base clock. It can also detect the zero cross of the external clock. Fig. 12-11 Block Diagram of Basic Timer 1 Clock selection block BTM1EXCK flag BTM1CK1 flag BTM1CK0 flag BTM1ZX flag 8 MHz Frequency divider Selector P1B3/TMIN (external clock) Zero-cross detection circuit Flipflop Set/clear BTM1CY flag Remarks 1. BTM1EXCK (bit 3 of basic timer 1 mode select register; see Fig. 12-12) specifies the base clock (internal or external clock). 2. BTM1ZX (bit 2 of basic timer 1 mode select register; see Fig. 12-12) specifies whether the zerocross detection circuit is on or off. 3. BTM1CK1 and BTM1CK0 (bits 1 and 0 of the basic timer 1 mode select register, respectively; see Fig. 12-12) specify the time interval at which the BTM1CY flag is set. 4. BTM1CY (bit 0 of the basic timer 1 carry flip-flop judge register; see Fig. 12-13) reflects the state of the flip-flop. 140 PD17068 12.3.2 Clock Selection Block The clock selection block divides the frequency of the system clock (8 MHz) or an external clock and specifies the time interval at which the BTM1CY flag is set, using the basic timer 1 mode select register. Either the system clock (8 MHz) or an external clock input at the P1B3/TMIN pin can be selected as the base clock of basic timer 1. When an external clock is selected, it is possible to select whether the zero-cross detection circuit is turned on or off. Fig. 12-12 shows the configuration and function of the basic timer 1 mode select register. Fig. 12-12 Configuration of the Basic Timer 1 Mode Select Register Flag symbol Register b3 B T M 1 E X C K b2 B T M 1 Z X b1 B T M 1 C K 1 b0 B T M 1 C K 0 Address Read/write Basic timer 1 mode select register 0BH R/W Specify the time interval at which the BTM1CY flag is set and whether the zerocross detection circuit is turned on or off. 0 0 0 0 1 1 1 1 x x x x 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x x x x 100 ms 5 ms 1 ms 125 s Divides the frequency of an external clock (at the P1B3/TMIN pin) by 5. Divides the frequency of an external clock (at the P1B3/TMIN pin) by 6. Divides the frequency of an external clock (at the P1B3/TMIN pin) by 5 (with the zero-cross detection circuit on). Divides the frequency of an external clock (at the P1B3/TMIN pin) by 6 (with the zero-cross detection circuit on). Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 Hold Remark x : Don't care 141 PD17068 12.3.3 Flip-Flop and BTM1CY Flag The flip-flop is set at constant intervals, and its state is detected using the BTM1CY flag of the basic timer 1 carry flip-flop judge register. The BTM1CY flag is reset to "0" by reading its contents into a window register using the PEEK instruction (Read & Reset). Even when power is supplied, the BTM1CY flag will not be set until a read instruction is executed. Once a read instruction is executed, the flag is set at constant intervals. Fig. 12-13 shows the configuration and function of the basic timer 1 carry flip-flop judge register. Fig. 12-13 Configuration of the Basic Timer 1 Carry Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 B T M 1 C Y Address Read/write Basic timer 1 carry flip-flop judge register 0 0 0 16H R & Reset Detects the state of the flip-flop. 0 1 The flip-flop is not set. The flip-flop is set. Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 1 1 12.3.4 Time Interval Error in Basic Timer 1 Similarly to basic timer 0, there are two types of errors in basic timer 1; one type is related to the detection time interval of the BTM1CY flag, and the other type can occur when the time interval at which the BTM1CY flag is set is changed. See Section 12.2.5. 142 PD17068 12.4 12.4.1 BASIC TIMER 2 Overview of Basic Timer 2 Fig. 12-14 shows the block diagram of basic timer 2. Basic timer 2 issues interrupt requests at constant intervals and sets (1) the IRQBTM2 flag. If an EI instruction has been executed and the IPBTM2 flag has been set, the basic timer 2 interrupt requests are accepted when the IRQBTM2 flag is set. (See Chapter 11.) Basic timer 2 can use an external clock input at the P1B3/TMIN pin as its base clock. It can also detect the zero cross of the external clock. Fig. 12-14 Block Diagram of Basic Timer 2 Clock selection block BTM2EXCK flag BTM2CK1 flag BTM2CK0 flag BTM2ZX flag 8 MHz Frequency divider Selector IRQBTM2 set signal P1B3/TMIN (external clock) Zero-cross detection circuit Remarks 1. BTM2EXCK (bit 3 of the basic timer 2 mode select register; see Fig. 12-15) specifies the base clock (internal or external clock). 2. BTM2ZX (bit 2 of the basic timer 2 mode select register; see Fig. 12-15) specifies whether the zero-cross detection circuit is on or off. 3. BTM2CK1 and BTM2CK0 (bits 1 and 0 of the basic timer 2 mode select register, respectively; see Fig. 12-15) specify the time interval at which the IRQBTM2 flag is set. 143 PD17068 12.4.2 Clock Selection Block The clock selection block divides the frequency of the system clock (8 MHz) or an external clock and specifies the time interval at which the IRQBTM2 flag is set, using the basic timer 2 mode select register. Either the system clock (8 MHz) or an external clock input at the P1B3/TMIN pin can be selected as the base clock of basic timer 2. When an external clock is selected, it is possible to select whether the zero-cross detection circuit is turned on or off. With an external clock (8 MHz), it is also possible to select that the zero-cross detection circuits is on or off. Fig. 12-15 shows the configuration and function of the basic timer 2 mode select register. Fig. 12-15 Configuration of the Basic Timer 2 Mode Select Register Flag symbol Register b3 B T M 2 E X C K b2 B T M 2 Z K b1 B T M 2 C K 1 b0 B T M 2 C K 2 Address Read/write Basic timer 2 mode select register 0AH R/W Specify the time interval at which the IRQBTM2 flag is set and whether the zerocross detection circuit is turned on or off. 0 0 0 0 1 1 1 1 x x x x 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x x x x 100 ms 5 ms 1 ms 125 s Divides the frequency of an external clock (at the P1B3/TMIN pin) by 5. Divides the frequency of an external clock (at the P1B3/TMIN pin) by 6. Divides the frequency of an external clock (at the P1B3/TMIN pin) by 5 (with the zero-cross detection circuit on). Divides the frequency of an external clock (at the P1B3/TMIN pin) by 6 (with the zero-cross detection circuit on). Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 Hold Remark x : Don't care 144 PD17068 12.4.3 Example of Using Basic Timer 2 A sample program follows. Example BR BTIMER: ADD SKT1 BR M1, #0001B CY BBB AAA ; Branches to AAA. ; Program address 0006H ; Adds 1 to M1. ; Tests the CY flag. ; Returns to the main routine if there is no carry. Process A BBB: EI RETI AAA: INITFLG NOT BTM2EXCK, NOT BTM2ZX, BTM2CK1, NOT BTM2CK0 ; Selects 1 ms as the basic timer 2 interrupt pulse. MOV SET1 EI LOOP: Process B BR LOOP M1, #000B IPBTM2 ; Clears the M1 contents to 0. ; Enables the basic timer 2 interrupt. ; Enables all interrupts. The above program performs process A at intervals of 1 ms. Note that when an interrupt request is accepted, subsequent interrupts are disabled. Also note that even if interrupts are disabled, the IRQBTM2 flag can be set to "1". In other words, if process A takes 1 ms or more, an interrupt request is accepted when a return is made by a RETI instruction, thus disabling process B from being performed. 12.4.4 Time Interval Error in Basic Timer 2 As explained in Section 12.4.3, if an EI instruction has been executed and basic timer 2 interrupts are enabled, an interrupt request is accepted each time the basic timer interrupt pulse rises. Therefore, a basic timer 2 error occurs only when: (1) An interrupt request is accepted for the first time after basic timer 2 interrupts are enabled. (2) An interrupt request is accepted for the first time after a time interval at which the IRQBTM2 flag is set is changed, that is after an interrupt pulse is changed, or (3) The IRQBTM2 is write-accessed. Fig. 12-16 shows the timing charts for errors that occur under the above conditions. 145 PD17068 Fig. 12-16 Basic Time 2 Error (1/2) (a) When basic timer 2 interrupts are enabled H Basic timer 2 interrupt pulse L tSET 1 IRQBTM2 flag 0 1 IRQBTM2 flag 0 EI INTE flip-flop DI EI Interrupt pending EI #$ SET1 IPBTM2 Interrupt accepted % Interrupt accepted Interrupt accepted When the IPBTM2 flag is set at point request is accepted immediately. # in the above chart to enable basic timer 2 interrupts, an interrupt A basic timer 2 error for this case is as follows: 0 (error) tSET When an EI instruction is issued at point basic timer 2 interrupt pulse rises. A basic timer 2 error for this case is as follows: 0 (error) tSET $ to enable interrupts, an interrupt occurs at point %, where the 146 PD17068 Fig. 12-16 Basic Time 2 Error (2/2) (b) When the basic timer 2 interrupt pulse is switched H Basic timer 2 interrupt internal pulse A L H Basic timer 2 interrupt internal pulse B L H Basic timer 2 interrupt pulse L 1 IRQBTM2 flag 0 1 IPBTM2 flag 0 EI INTE flip-flop DI EI Interrupt accepted Basic timer 2 interrupt pulse switched # % Basic timer 2 interrupt pulse $ EI EI switched EI Interrupt accepted Interrupt accepted request is not accepted at point # in the above chart, an interrupt $ because the basic timer 2 interrupt pulse does not rise. When the basic timer 2 interrupt pulse is switched from B to A at point %, an interrupt request is accepted Even when the basic timer 2 interrupt pulse is switched from A to B at point (c) When the IRQBTM2 flag is manipulated H Basic timer 2 interrupt pulse L 1 IRQBTM2 flag 0 1 IPBTM2 flag 0 EI INTE flip-flop DI EI Interrupt accepted immediately, because the basic timer 2 interrupt pulse rises. # EI $ CLR1 IRQBTM2 Interrupt not accepted Interrupt accepted SET1 IRQBTM2 Interrupt accepted When the IRQBTM2 flag is set to "1" at point immediately. If the IRQBTM2 flag is reset to "0" at point interrupt is not accepted. # in the above chart, an interrupt request is accepted 147 $ at the same time the basic timer 2 interrupt pulse rises, an PD17068 12.4.5 Cautions for Using Basic Timer 2 When basic timer 2 is used in a program that runs at constant intervals once power is supplied (after poweron reset), such as a clock program, the program must complete interrupt handling related to basic timer 2 within a certain period of time. This is explained below, using an example. Example M1 TIMER MEM DAT BR ORG TIMER ADD SKT1 BR ; M1, #1010B CY EI_RETI 0.10H 0006H START ; 1 ms counter ; Interrupt vector address symbol definition ; Branches to START. ; Program address (0006H) ; Add 1010B to the M1 contents. ; Clock processing if a carry occurs ; Makes a return if there is no carry. # EI Clock processing EI_RETI : RETI START : CLR2 BTM0CK1, BTM0CK0 ; Built-in macro ; Specifies that the BTM0CY flag is set at ; intervals of 100 ms. CLR4 BTM2EXCK, BTM2ZX, BTM2CK1, BTM2CK0 ; Built-in macro ; Set the basic timer 2 interrupt time to ; 100 ms. SET1 EI LOOP: Process A BR LOOP IPBTM2 ; Enables basic timer 2 interrupts. ; Enables all interrupts. In the above example, the clock processing is repeated at intervals of 1 second, while process A is performed. As shown in Fig. 12-17 (a), when the CE pin goes from a low to a high, a CE reset occurs at the same time the BTM0CY flag set pulse rises. If a basic timer 2 interrupt is requested at the same time the BTM0CY flag is set, a CE reset takes preference. When a CE reset occurs, it automatically resets a basic timer 2 interrupt request (IRQBTM2), hence failing to perform timer processing for one cycle. 148 PD17068 To solve this problem, as shown in Fig. 12-17 (b), a gap in time is provided between when the BTM0CY flag set pulse rises and when the basic timer 2 interrupt pulse rises. In this example, the clock processing is completed with 550 s in order to eliminate a possibility that the occurrence of a CE reset prohibits acceptance of a basic timer 2 interrupt request. In other words, you should complete your basic timer 2 interrupt handling within 550 s, if you want to enable basic timer 2 interrupts even at a CE reset. If 125 s has been selected as the basic timer 2 interrupt time interval, however, the interrupt handling must be completed within 75 s. A gap in time is also provided between the BTM0CY flag set pulse and the BTM1CY flag set pulse. Fig. 12-17 Timing Chart (a) H CE pin L H BTM0CY flag set pulse L H L Basic timer 2 interrupt pulse Basic timer 2 interrupt A CE reset occurs at this point, thus failing to accept a basic timer 2 interrupt for one cycle, because the BTM0CY flag set pulse rises. (b) H CE pin L Gap in time (550 s in this case) H L H L BTM0CY flag set pulse Basic timer 2 interrupt pulse Basic timer 2 interrupt Basic timer 2 interrupt CE reset Because there is a time gap of 550 s between when the basic timer 2 interrupt pulse rises and when the BTM0CY flag set pulse rises, a CE reset will not hamper a normal timer process provided that the basic timer 2 interrupt handling is completed within 550 s. 149 PD17068 12.5 12.5.1 TIMER 0 Overview of Timer 0 Fig. 12-18 shows the block diagram of timer 0. Timer 0 is realized by dividing the frequency of the basic clock (100 kHz or 20 kHz) using the 12-bit counter and by comparing the count in the 12-bit counter with a previously set value. Fig. 12-18 Block Diagram of Timer 0 Clock selection block Count block TM0CK flag TM0RES flag TM0RPT flag TM0EN flag DBF 12 TM0OVF flag Set/clear Overflow IRQGRP0 set signal 8 MHz Frequency divider Selector Timer 0 counter (TM0C) Match Match detection circuit IRQTM0 set signal Timer 0 modulo register (TM0M) 12 DBF Remarks 1. TM0CK (bit 0 of timer 0 clock select register; see Fig. 12-19) specifies the basic clock frequency. 2. TM0EN (bit 0 of timer 0 control register; see Fig. 12-20) specifies whether to start or stop timer 0. 3. TM0RES (bit 1 of timer 0 control register; see Fig. 12-20) specifies whether to reset the timer 0 counter. 4. TM0RPT (bit 2 of timer 0 control register; see Fig. 12-20) selects the modulo count mode or free-run count mode. 5. TM0OVF (bit 0 of timer 0 overflow register; see Fig. 12-21) detects when the timer 0 counter overflows. 150 PD17068 12.5.2 Clock Selection Block The clock selection block specifies the basic clock pulse used to run the timer 0 counter. Two types of pulses can be selected as the basic clock pulse using the TM0CK flag. Fig. 12-19 shows the configuration and function of the timer 0 clock select register. Fig. 12-19 Configuration of the Timer 0 Clock Select Register Flag symbol Register b3 b2 b1 b0 T M 0 C K Address Read/write Timer 0 clock select register 0 0 0 09H R/W Specifies the basic clock for timer 0. 0 0 100 kHz (10 s) 20 kHz (50 s) Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 Hold 151 PD17068 12.5.3 Count Block The count block counts the basic clock pulses using the 12-bit timer 0 counter, and outputs the count. It also issues an interrupt request if the count matches the value in the timer 0 modulo register. The TM0EN flag specifies whether to start or stop the basic clock pulse supplied to the timer 0 counter. The TM0RES flag can reset the timer 0 counter. The timer 0 counter is not automatically reset when its content matches the value in the timer modulo register. The TM0RPT flag selects the modulo count or free-run count mode. In the free-run count mode, when the content of the timer 0 counter matches the content of the timer modulo register, timer 0 counter continues to be incremented without being reset. In the module count mode, when the content of the timer 0 counter matches the content of the timer modulo register, timer 0 counter continues to be incremented after reset. The TM0OVF flag can be used to detect when the counter overflows. It issues an interrupt request when an overflow occurs. The timer 0 counter can be read- and write-accessed through the data buffer. Fig. 12-20 shows the configuration and function of the timer 0 control register. Fig. 12-21 shows the configuration and function of the timer 0 overflow register. Figs. 12-22 and 12-23 show the configuration of the timer 0 counter and timer 0 modulo register, respectively. Fig. 12-20 Configuration of the Timer 0 Control Register Register b3 Flag symbol b2 T M 0 R P T b1 T M 0 R E S b0 T M 0 E N Address Read/write Timer 0 control register 0 0DH R/W (for bit 0, W only) Specifies whether to start or stop timer 0. 0 1 Stop. Start. Resets the timer 0 counter. 0 1 Do not reset. Reset. Selects a timer 0 mode. 0 1 Free-run count mode Modulo count mode Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 Hold 0 0 152 PD17068 Fig. 12-21 Configuration of the Timer 0 Overflow Register Flag symbol Register b3 b2 b1 b0 T M 0 O V F Address Read/write Timer 0 overflow register 0 0 0 0EH R Detects when the timer 0 counter overflows. 0 1 No overflow Overflow Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 Hold Fig. 12-22 Configuration of the Timer 0 Counter Data buffer DBF3 DBF2 DBF1 Transfer data DBF0 GET 16 Peripheral register Register b15 b14 b13 b12 b11 b10 b9 M S B b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address L S B Timer 0 counter Effective data TM0C 47H Count in the timer 0 counter 0 * Free-run count mode The counter goes up to FFFH, then stops on the next clock pulse. x * Modulo count mode The counter goes up to the value set in the timer 0 modulo register, then is reset back to 000H on the next clock and continues counting. 212 - 1 (FFFH) Fixed to "0" 153 PD17068 Fig. 12-23 Configuration of the Timer 0 Modulo Register Data buffer DBF3 DBF2 Transfer data GET 16 PUT Peripheral register Register Timer 0 modulo register b15 b14 b13 b12 b11 b10 b9 M S B b8 b7 b6 b5 b4 b3 b2 b1 b0 L S B Symbol Peripheral address DBF1 DBF0 Effective data TM0M 46H Value set in the timer 0 modulo register 0 1 Must not be set. x Modulo data 212 - 1 (FFFH) Fixed to "0" 154 PD17068 12.5.4 Example of Using Timer 0 Example 1. Module count mode BR ORG TMINT: Process A EI RETI START: CLR1 MOV MOV MOV PUT SET1 EI SET3 LOOP: Main process BR LOOP TM0RPT, TM0RES, TM0EN TMCK0 ;Specifies 10 s as the count clock. DBF2, #50 SHR 8 AND 0FH DBF1, #50 SHR 4 AND 0FH DBF0, #50 AND 0FH TM0M, DBF IPTM0 0004H START This program performs process A at intervals of 500 s. Process A must be completed within 500 s. 155 PD17068 Example 2. Free-run count mode BR . . . START: CLR1 CLR1 SET2 TMCK0 ;Specifies 10 s as the count clock. TM0RPT TM0RES, TM0EN START Process A SKF1 BR GET TM0OVF Overflow detected DBF, TM0C . . . Overflow detected: . . . This program measures the time required to perform process A. It can measure a period of time ranging from 10 s to 40950 s. (This program cannot measure a period longer than 40950 s. A branch should be made to another routine.) The above sample program can be used to measure the pulse width of a remote control signal. The modulo count mode is convenient in issuing interrupt requests at constant intervals, while the freerun count mode is useful to measure total time. 12.5.5 Time Interval Error in Timer 0 Timer 0 encounters up to one basic pulse's worth of time interval error under the following conditions. (1) When the TM0EN flag is manipulated When the TM0EN flag is set, 0 to +1 pulse's worth of error occurs. When the TM0EN flag is reset, 0 to -1 pulse's worth of error occurs. (2) When the counter is reset during operation When the counter is reset, 0 to +1 pulse's worth of error occurs. (3) When the basic clock is switched during operation of the counter 0 to +1 newly selected pulse's worth of error occurs. 12.5.6 Cautions for Using Timer 0 A timer 0 interrupt request may occur simultaneously with other timer interrupt requests or a CE reset. If it is necessary to update the timer even at a CE reset, do not use timer 0. Use basic timer 0, instead. 156 PD17068 12.6 12.6.1 TIMER 1 Overview of Timer 1 Fig. 12-24 shows the block diagram of timer 1. Timer 1 is realized by dividing the frequency of the basic clock (100 kHz, 10 kHz, 20 kHz, or 1 kHz) using the 8-bit counter and by comparing the count in the 8-bit counter with a previously set value. Fig. 12-24 Block Diagram of Timer 1 Clock selection block TM1CK1 flag TM1CK0 flag Count block TM1RES flag TM1EN flag DBF 8 8 MHz Frequency divider Selector Timer 1 counter (TM1C) Match detection circuit Match IRQTM1 set signal Timer 1 modulo register (TM1M) 8 DBF Remarks 1. TM1CK1 and TM1CK0 (bits 1 and 0 of timer 1 clock select register; Fig. 12-25) specify the basic clock frequency. 2. TM1EN (bit 0 of timer 1 control register; Fig. 12-26) specifies whether to start or stop timer 1. 3. TM1RES (bit 1 of timer 1 control register; Fig. 12-26) specifies whether to reset the timer 1 counter. 157 PD17068 12.6.2 Clock Selection Block The clock selection block specifies the basic clock pulse used to run the timer 1 counter. Four types of pulses can be selected as the basic clock pulse using the TM1CK0 and TM1CK1 flags. Fig. 12-25 shows the configuration and function of the timer 1 clock select register. Fig. 12-25 Configuration of the Timer 0 Clock Select Register Flag symbol Register b3 b2 b1 T M 1 C K 1 b0 T M 1 C K 0 Address Read/write Timer 1 clock select register 0 0 1AH R/W Specifies the basic clock for timer 1. 0 0 1 1 0 1 0 1 1 kHz (1 ms) 10 kHz (100 s) 20 kHz (50 s) 100 kHz (10 s) Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Hold 158 PD17068 12.6.3 Count Block The count block counts the basic clock pulses using the 8-bit timer 1 counter, and outputs the count. It also issues an interrupt request if the count matches the value in the timer 1 modulo register. The TM1EN flag can start or stop the basic clock pulse supplied to the timer 1 counter. The TM1RES flag can reset the timer 1 counter. The timer 1 counter is not automatically reset when its content matches the value in the timer 1 modulo register. The timer 1 counter can be read- and write-accessed through the data buffer. Fig. 12-26 shows the configuration and function of the timer 1 control register. Figs. 12-27 and 12-28 show the configuration and function of the timer 1 counter and timer 1 modulo register, respectively. Fig. 12-26 Configuration of the Timer 1 Control Register Flag symbol Register b3 b2 b1 T M 1 R E S b0 T M 1 E N Address Read/write Timer 1 control register 0 0 1BH R/W Specifies whether to start or stop timer 1. 0 1 Stop. Start. Specifies whether to reset timer 1 counter.Note 0 1 Do not reset. Reset. Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Hold Note This is effective only at write access. "0" is always read out. 159 PD17068 Fig. 12-27 Configuration of the Timer 1 Counter Data buffer DBF3 Hold DBF2 Hold DBF1 DBF0 Transfer data GET 8 Peripheral register Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address TM1C 06H Timer 1 counter Effective data Reads the count in the timer 1 counter. 0 x Count 0FFH Fig. 12-28 Configuration of the Timer 1 Modulo Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET 8 PUT Peripheral register Register Timer 1 modulo register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address TM1M 05H DBF0 Effective data Specify the data for the timer 1 modulo register. 0 Must not be set. x Modulo data 0FFH 160 PD17068 12.6.4 Time Interval Error in Timer 1 Timer 1 encounters up to one basic pulse's worth of time interval error under the following conditions. (1) When the TM1EN flag is manipulated When the TM1EN flag is set, 0 to +1 pulse's worth of error occurs. When the TM1EN flag is reset, 0 to -1 pulse's worth of error occurs. (2) When the counter is reset during operation When the counter is reset, 0 to +1 pulse's worth of error occurs. (3) When the basic clock is switched during operation of the counter 0 to +1 newly selected pulse's worth of error occurs. 12.6.5 Cautions for Using Timer 1 A timer 1 interrupt request may occur simultaneously with other timer interrupt requests or a CE reset. If it is necessary to update the timer even at a CE reset, do not use timer 1. Use basic timer 0, instead. 161 PD17068 12.7 12.7.1 CLOCK TIMER Overview of the Clock Timer Fig. 12-29 shows the block diagram of the clock timer. The clock timer is realized by counting seconds, minutes, hours, and days using a clock pulse and by reading out the counts. The clock pulse is generated by dividing a frequency of 32 kHz. The clock timer can also be used as an ordinary timer by detecting a flip-flop that is set at 128 or 8 Hz by software. Fig. 12-29 Block Diagram of the Clock Timer Clock frequency divider block WTMHLD flag DBF WTM 128Hz flag WTM 8Hz flag Count block XTSEL flag 128 Hz carry flip-flop 8 Hz carry flip-flop Seconds set register (WTMSEC) Minutes set register (WTMMIN) Hours set register (WTMHR) Days set register (WTMDAY) 32 kHz oscillator Frequency divider Seconds counter Minutes counter Hours counter Days counter CKOSEL flag Counter reset Reset control To port 1B 1 0 P1B1/CKOUT WTMRES0 to WTMRES3 flags Reset control block Remarks 1. XTSEL (bit 0 of the clock timer mode register; see Fig. 12-32) selects the function of the P0D0/ ADC1/XTOUT and P0D1/ADC2/XTIN pins. 2. CKOSEL (bit 1 of the clock timer mode register; see Fig. 12-32) specifies whether to output the clock timer adjustment oscillator. 3. WTM128HZ (bit 0 of the clock timer 128 Hz carry register; see Fig. 12-30) detects the state of the 128 Hz carry flip-flop. 4. WTM8HZ (bit 0 of the clock timer 8 Hz carry register; see Fig. 12-31) detects the state of the 8 Hz carry flip-flop. 5. WTMHLD (bit 3 of the clock timer mode register; see Fig. 12-32) specifies whether to hold the clock timer. 6. WTMRES0 to WTMRES3 (bits 0 to 3 of the clock timer reset register; see Fig. 12-36) specifies whether to reset the clock timer. 162 PD17068 12.7.2 Clock Frequency Divider Block The clock frequency block divides a frequency of 32 kHz to generate a clock pulse used for the clock timer. The clock frequency block can also detect the WTM128HZ flag (bit 0 of the clock timer 128 Hz carry register) and the WTM8HZ flag (bit 0 of the clock timer 8 Hz carry register). Setting (1) the WTMHLD flag of the clock timer mode register can hold the clock output at a point where 500 ms worth of frequency division is completed. Figs. 12-30 and 12-31 show the configuration and function of the clock timer 128 Hz carry register and clock timer 8 Hz carry register. Fig. 12-32 shows the configuration and function of the clock timer mode register. Fig. 12-30 Configuration of the Clock Timer 128 Hz Carry Register Flag symbol Register b3 b2 b1 b0 W T M 1 2 8 H Z Address Read/write Clock timer 128 Hz carry register 0 0 0 1EH R & Reset Detects the state of the 128 Hz carry flip-flop. 0 1 Reset. Set. Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 Hold Hold 163 PD17068 Fig. 12-31 Configuration of the Clock Timer 8 Hz Carry Register Flag symbol Register b3 b2 b1 b0 W T M 8 H Z Address Read/write Watch timer 8 Hz carry register 0 0 0 1DH R & Reset Detects the state of the 8 Hz carry flip-flop. 0 1 Reset. Set. Fixed to "0" Upon reset Power-on Clock stop CE 0 0 0 0 Hold Hold 164 PD17068 Fig. 12-32 Configuration of the Clock Timer Mode Register Flag symbol Register b3 W T M H L D b2 b1 C K O S E L b0 X T S E L W (R/W for bit 0 only) Address Read/write Clock timer mode register 0 06H Selects the function of the P0D0/ADC1/XTOUT and P0D1/ADC2/XTIN pins. 0 1 Operation as a port Operation as a connection pin for the clock timer oscillator Specifies whether to output the clock timer adjustment oscillator. 0 1 No output. Output from the P1B1/CKOUT. Fixed to "0" Specifies whether to hold the clock timer. 0 1 Do not hold. Hold. Upon reset Power-on Clock stop CE 0 Hold Hold 0 0 0 0 Hold 0 Hold 12.7.3 Count Block The count block counts clock pulses, which are generated by the clock frequency division block, using four 8-bit counters. The clock timer consists of a seconds counter (sexagesimal), minutes counter (sexagesimal), hours counter (24-ary), days counter (septinary). These counters are reset by the reset control block (see Section 12.7.4). Each counter can be write- and read-accessed through the data buffer. Figs. 12-33 to 12-35 show the configuration and function of the registers to control the count block. 165 PD17068 Fig. 12-33 Configuration of the Seconds and Minutes Set Registers Data buffer DBF3 Don't care DBF2 Don't care DBF1 DBF0 Transfer data GET 8 PUT Peripheral register Register Seconds set register Minutes set register b7 0 b6 0 b5 b4 b3 b2 b1 b0 Symbol Peripheral address WTMSEC 1AH Effective data 0 0 Effective data WTMMIN 1BH Counts in the seconds and minutes counters 0 Incremented at every second (or every minute for the minutes counter) with a carry generated at every 60 seconds (or every 60 minutes for the minutes counter)--sexagesimal counters. * At read access Current count in each counter * At write access Each counter is initialized. The counters must be reset before a write access. x 59 (3BH) 60 (3CH) Values which do not exist at a read access. If any of these values is written to the counters, their contents become undefined. 63 (3FH) Fixed to "0" 166 PD17068 Fig. 12-34 Configuration of the Hours Set Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 DBF0 Transfer data GET 8 PUT Peripheral register Register Hours set register b7 0 b6 0 b5 0 b4 b3 b2 b1 b0 Symbol Peripheral address WTMHR 1CH Effective data Count in the hours counter 0 Incremented at every hour with a carry generated at every 24 hours (24-ary counter). * At read access Current count in the counter * At write access The counter is initialized. The counter must be reset before a write access. x 23 (17H) 24 (18H) Values which do not exist at a read access. If any of these values is written to the counter, its content becomes undefined. 31 (1FH) Fixed to "0" 167 PD17068 Fig. 12-35 Configuration of the Days Set Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET 8 PUT Peripheral register Register Days set register b7 0 b6 0 b5 0 b4 0 b3 0 b2 b1 b0 Symbol Peripheral address 1DH DBF0 Effective data WTMDAY Count in the days counter 0 Incremented at every day with a carry generated at every 7 days (septinary counter). * At read access Current count in the counter * At write access The counter is initialized. The counter must be reset before a write access. x 6 (6H) Values which do not exist at a read access. If any of these values is written to the counter, its content becomes undefined. 7 (7H) Fixed to "0" 168 PD17068 12.7.4 Reset Control Block The clock timer reset register specifies whether to set or reset the clock timer. Fig. 12-36 shows the configuration and function of the clock timer reset register. Fig. 12-36 Configuration of the Clock Timer Reset Register Flag symbol Register b3 W T M R E S 3 b2 W T M R E S 2 b1 W T M R E S 1 b0 W T M R E S 0 Address Read/write Clock timer reset register 14H R/W Specifies whether to reset the clock timer basic clock, seconds, minutes, hours, and days counters. 0 1 Do not reset. Reset. Specifies whether to reset the clock timer basic clock. 0 1 Do not reset. Reset. Specifies whether to reset the seconds, minutes, and hours counters. 0 1 Do not reset. Reset. Specifies whether to reset the days counter. 0 1 Do not reset. Reset. Upon reset Power-on Clock stop CE 0 0 0 0 Hold Hold 169 PD17068 12.7.5 32 kHz Oscillator and Oscillation Frequency Adjustment The 32 kHz oscillator generates a 32 kHz clock pulse for the clock timer. When using the clock timer, set the XTSEL flag of the clock timer mode register to specify the P0D0/ADC1/ XTOUT and P0D1/ADC2/XTIN pins as the clock timer oscillator connection pins. The 32 kHz clock pulse is supplied at the P1B1/CKOUT pin for oscillation frequency adjustment. To use this pin for oscillation frequency adjustment output, set the CKOSEL flag of the clock timer mode register. See Fig. 12-32 for the configuration and function of the clock timer mode register. 12.7.6 Cautions for Using the Clock Timer (1) Rewriting the counts in the counters When you want to rewrite the contents of the seconds, minutes, hours, and days counters, previously reset them. If the contents of these counters have not been reset, a normal value cannot be written to the counters when the count, such as seconds, minutes, hours, or days, is a non-zero or a nonexisting value (for example, 61 in the seconds counter). (2) Reset control While the WTMRESn (n = 0 to 3) is "1", the counter corresponding to the flag will not work. If you want to reset any of these counters, first set the corresponding WTMRES flag to "1" and reset the counter, then reset the flag to "0" again. 170 PD17068 13. A/D CONVERTER 13.1 OUTLINE OF A/D CONVERTER Fig. 13-1 outlines the A/D converter. The A/D converter compares an analog voltage applied to the ADC0-ADC7 pins with an internal reference voltage, then converts the analog voltage to a 6-bit digital signal by evaluating the result of comparison with software. The result of comparison is detected using the ADCCMP flag. The successive approximation system is used for comparison. Fig. 13-1 Schematic Diagram of A/D Converter ADCCH2 flag ADCCH1 flag ADCCH0 flag ADC0 P0D0/ADC1/XTOUT P0D1/ADC2/XTIN P0D2/ADC3 P0D3/ADC4 P1C0/ADC5 P1C1/ADC6 P1C2/ADC7 Input switching block Compare block Set/reset ADCCMP flag DBF ADCEN flag 6 Reference voltage generation block (D/A converter based on the R string method) Start/stop control block Remarks 1. ADCCH0-2 (A/D converter channel select register bits 0 to 2): Select a pin used for the A/D converter. (See Fig. 13-3.) 2. ADCCMP (A/D converter control register bit 0): Detects the result of comparison. (See Fig. 13-5.) 3. ADCEN (A/D converter control register bit 3): Detects comparison execution and comparison status. (See Fig. 13-5.) 171 PD17068 13.2 INPUT SWITCHING BLOCK Fig. 13-2 shows the configuration of the input switching block. The input switching block selects a pin according to the setting of the A/D converter channel select register. If the P1C0/ADC5-P1C2/ADC7 pins are set as general-purpose output ports at this time, output signals are output on these pins and the P1C3 pin. When any of these pins is to be used for the A/D converter, the pin must be set as an input port by using the port IC group I/O select register. In this case, the pins not used for the A/D converter and the P1C3 pin are set as general-purpose input ports. Only one pin can be used for the A/D converter at a time. Port 0D contains a pull-down resistor. However, the pull-down resistor is turned off when the port is selected for the A/D converter. At this time, the pull-down resistors of the pins not selected remain on. Fig. 13-3 shows the format and function of the A/D converter channel select register. Fig. 13-2 Configuration of Input Switching Block ADCCH2 flag ADCCH1 flag ADCCH0 flag Selector ADC0 P0D0/ADC1/XTOUT P0D1/ADC2/XTIN P0D2/ADC3 P0D3/ADC4 P1C0/ADC5 P1C1/ADC6 P1C2/ADC7 Compare block VADCIN I/O port 172 PD17068 Fig. 13-3 Format of A/D Converter Channel Select Register Flag symbol Register b3 b2 A D C C H 2 b1 A D C C H 1 b0 A D C C H 0 Address Read/write A/D converter channel select register 0 21H R/W Selects a pin used for the A/D converter. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADC0 pin P0D0/ADC1/XTOUT pin P0D1/ADC2/XTIN pin P0D2/ADC3 pin P0D3/ADC4 pin P1C0/ADC5 pin P1C1/ADC6 pin P1C2/ADC7 pin Fixed to 0 Upon reset Power-on Clock stop CE * = Hold 0 0 0 * 0 0 * 0 0 * 173 PD17068 13.3 COMPARE VOLTAGE GENERATION BLOCK AND COMPARE BLOCK Fig. 13-4 shows the configuration of the reference voltage generation block and compare block. According to the 6-bit data set in the A/D converter data register, the reference voltage generation block switches between tap decoders to generate 64 types of reference voltage VREF. This means that the reference voltage generation block is a D/A converter based on the R string method. The power supply for the R string method has the same potential as VDD of the device. The compare block compares the voltage VADCIN applied to a pin with the reference voltage VREF to determine which is larger. Fig. 13-5 and Fig. 13-6 show the formats and functions of the A/D converter control register flags and A/D converter data register. Table 13-1 provides a list of reference voltages. Fig. 13-4 Configuration of Reference Voltage Generation Block and Compare Block 1/2 VDD VADCIN DBF VREF 2 pF Comparator ADCCMP flag A/D converter data register (ADCR) Tap decoder 0 1 2 62 63 VDD 1 R 2 R R 3 R 2 Start/stop control block ADCEN flag 174 PD17068 Fig. 13-5 Format of A/D Converter Control Register Register A D C E N Flag symbol b3 b2 b1 b0 A D C C M P Address Read/write A/D converter control register 0 0 24H R/W R for bit 0 only Detects the result of comparison by the A/D converter. 0 1 VADCIN < VREF VADCIN > VREF Fixed to 0 Detects the comparison execution and comparison status of the A/D converter. In write operation 0 1 No change Comparison executed In read operation Comparison completed Comparison in progress Upon reset Power-on Clock stop CE 0 0 0 * = Undefined ** = Hold 0 0 * ** ** 175 PD17068 Fig. 13-6 Format of A/D Converter Data Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET 8 PUT Peripheral register Register A/D converter data register b7 0 b6 0 b5 b4 b3 b2 b1 b0 Symbol Peripheral address ADCR 02H DBF0 Valid data Sets an A/D converter reference voltage. 0 1 VREF = 0 V x VREF = x - 0.5 x VDD (V) 64 FFH Fixed to 0 176 PD17068 Table 13-1 Values in A/D Converter Data Register and Reference Voltages Data set in ADCR Decimal (DEC) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal (HEX) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Reference voltage Logical voltage Unit: x VDD V 0 0.5/64 1.5/64 2.5/64 3.5/64 4.5/64 5.5/64 6.5/64 7.5/64 8.5/64 9.5/64 10.5/64 11.5/64 12.5/64 13.5/64 14.5/65 15.5/64 16.5/64 17.5/64 18.5/64 19.5/64 20.5/64 21.5/64 22.5/64 23.5/64 24.5/64 25.5/64 26.5/64 27.5/64 28.5/64 29.5/64 30.5/64 When VDD = 5 V Unit: V 0 0.039 0.117 0.195 0.273 0.352 0.430 0.508 0.586 0.664 0.742 0.820 0.898 0.977 1.055 1.133 1.211 1.289 1.367 1.445 1.523 1.602 1.680 1.758 1.836 1.914 1.992 2.070 2.148 2.227 2.305 2.383 Data set in ADCR Decimal Hexadecimal (DEC) (HEX) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Reference voltage Logical voltage Unit: x VDD V 31.5/64 32.5/64 33.5/64 34.5/64 35.5/64 36.5/64 37.5/64 38.5/64 39.5/64 40.5/64 41.5/64 42.5/64 43.5/64 44.5/64 45.5/64 46.5/64 47.5/64 48.5/64 49.5/64 50.5/64 51.5/64 52.5/64 53.5/64 54.5/64 55.5/64 56.5/64 57.5/64 58.5/64 59.5/64 60.5/64 61.5/64 62.5/64 When VDD = 5 V Unit: V 2.461 2.539 2.617 2.695 2.773 2.852 2.930 3.008 3.086 3.164 3.242 3.320 3.398 3.477 3.555 3.633 3.711 3.789 3.867 3.945 4.023 4.102 4.180 4.258 4.336 4.414 4.492 4.570 4.648 4.727 4.805 4.883 177 PD17068 13.4 COMPARE TIMING CHART When a compare operation is completed, the ADCEN flag is automatically reset to 0. This means that the ADCEN flag is detected after the ADCEN flag is set, and the result of comparison (ADCCMP flag) is read when the ADCEN flag is reset. Accordingly, the time required for one compare operation is three-instruction execution time (6 s). Fig. 13-7 indicates the timing chart. Fig. 13-7 Timing of A/D Converter Compare Operation Instruction cycle Sample and hold ADCEN flag ADCCMP flag Result of comparison 13.5 A/D CONVERTER PERFORMANCE Table 13-2 indicates the performance of the A/D converter. Table 13-2 Performance of A/D Converter Item Resolution Input voltage range Quantization error Performance 6 bits 0-VDD 1 2 LSB x VDD Over-range 62.5 64 Errors associated with offset, gain, nonlinearity, etc. 3 LSB Note 2 Note A quantization error is included. 178 PD17068 13.6 13.6.1 USING A/D CONVERTER Comparison with One Reference Voltage An example of program is described below. Example A comparison is made between the input voltage VADCIN applied to the ADC0 pin and the reference voltage VREF ((31.5/64) x VDD). When VADCIN > VREF, a branch to AAA occurs. When VADCIN < VREF, a branch to BBB occurs. INIT: ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 FLG FLG FLG FLG FLG FLG FLG FLG 0.0EH.3 0.0EH.2 0.0EH.1 0.0EH.0 0.0FH.3 0.0FH.2 0.0FH.1 0.0FH.0 ; Dummy ; Dummy ; Defines each bit of the data buffer as an ADCR data setting flag. INITFLG NOT ADCCH3, NOT ADCCH2, NOT ADCCH1, NOT ADCCH0 ; Sets the ADC0 pin for the A/D converter. START: INITFLG NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0 INITFLG NOT ADCR7, NOT ADCR6, NOT ADCR5, NOT ADCR4 PUT SET1 SKF1 BR SKT1 BR BR ADCR, DBF ADCEN ADCEN $-1 ADCCMP AAA BBB ; Detects the ADCCMP flag, then ; Branches to AAA when the result of comparison is false. ; Branches to BBB when the result of comparison is true. ; Sets (31.5/64) x VDD as the reference voltage VREF. ; Starts comparison. ; Detects compare operation in progress. 179 PD17068 13.6.2 Successive Approximation Based on the Binary Search Method In one compare operation, the A/D converter can make a comparison with only one reference voltage. This means that successive approximation needs to be programmed for conversion of an analog voltage to a digital signal. If the processing time of a successive approximation program varies from one input voltage to another, processing of other programs may be adversely affected. In such a case, the binary search method described in (1) to (3) below is useful. (1) Concept of binary search The concept of binary search is described below. First, VDD/2 is set as a reference voltage. Then, a comparison is made by adding a voltage of VDD/4 when the result of comparison is true (when a higher level is applied), or subtracting a voltage of VDD/4 when the result of comparison is false (when a lower level is applied). Similarly, comparisons are made sequentially adding or subtracting VDD/8, VDD/16, VDD/32, and VDD/64 in this order. If the result of comparison is false at the sixth stage, VDD/64 is subtracted finally. 1 H H H 3/4 H L Reference voltage (x VDD) 1/2 H L 1/4 L H 1/8 L 0 3/16 1/16 3/8 L 5/16 13/16 L H 25/32 L 49/64 L 51/64 L 5/8 L H 11/16 L 9/16 7/16 H 27/32 L 53/64 L 29/32 7/8 L 13/16 15/16 H L H 59/64 L 57/64 L 55/64 L 15/16 H 31/32 L 61/64 L H 63/64 L 1 63/64 62/64 61/64 60/64 59/64 58/64 57/64 56/64 55/64 54/64 53/64 52/64 51/64 50/64 49/64 48/64 Stage Stage Stage Stage Stage Stage 1/64 is subtracted when the result of comparison is false. 180 PD17068 (2) Flowchart of the binary search method Start Initialization ADCR 100000B ADCCMP=1? N Y : Sets a pin to be used. : Sets the reference voltage to VDD/2. : Detects the result of comparison, then Reset b5 of ADCR Set b4 of ADCR ADCCMP=1? N Y : Subtracts VDD/2 from the reference voltage when the flag is set to 0. : Adds VDD/4 to the reference voltage when the flag is set to either 0 or 1. : Detects the result of comparison, then Reset b4 of ADCR Set b3 of ADCR ADCCMP=1? N Y : Subtracts VDD/4 from the reference voltage when the flag is set to 0. : Adds VDD/8 to the reference voltage when the flag is set to either 0 or 1. : Detects the result of comparison, then Reset b3 of ADCR Set b2 of ADCR ADCCMP=1? N Y : Subtracts VDD/8 from the reference voltage when the flag is set to 0. : Adds VDD/16 to the reference voltage when the flag is set to either 0 or 1. : Detects the result of comparison, then Reset b2 of ADCR Set b1 of ADCR ADCCMP=1? N Y : Subtracts VDD/16 from the reference voltage when the flag is set to 0. : Adds VDD/32 to the reference voltage when the flag is set to either 0 or 1. : Detects the result of comparison, then Reset b1 of ADCR Set b0 of ADCR ADCCMP=1? N Y : Subtracts VDD/32 from the reference voltage when the flag is set to 0. : Adds VDD/64 to the reference voltage when the flag is set to either 0 or 1. : Detects the result of comparison, then Reset b0 of ADCR Detect contents of ADCR : Subtracts VDD/64 from the reference voltage when the flag is set to 0. : Ends conversion when the flag is set to 1. End 181 PD17068 (3) Example of program based on the binary search method (a) Method with a short conversion time INIT: ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 FLG FLG FLG FLG FLG FLG FLG FLG 0.0EH.3 0.0EH.2 0.0EH.1 0.0EH.0 0.0FH.3 0.0FH.2 0.0FH.1 0.0FH.0 ; Dummy ; Dummy ; Defines each bit of the data buffer as an ADCR data setting ; flag. ; ; ; ; INITFLG NOT ADCCH3, NOT ADCCH2, NOT ADCCH1, NOT ADCCH0 ; Sets the ADC0 pin for the A/D converter. START: INITFLG NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0 INITFLG NOT ADCR7, NOT ADCR6, NOT ADCR5, NOT ADCR4 PUT SET1 SKF1 BR SKT1 CLR1 SET1 PUT SET1 SKF1 BR SKT1 CLR1 SET1 PUT SET1 SKF1 BR SKT1 CLR1 SET1 PUT SET1 SKF1 BR ADCR, DBF ADCEN ADCEN $-1 ADCCMP ADCR5 ADCR4 ADCR, DBF ADCEN ADCEN $-1 ADCCMP ADCR4 ADCR3 ADCR, DBF ADCEN ADCEN $-1 ADCCMP ADCR3 ADCR2 ADCR, DBF ADCEN ADCEN $-1 ; Starts comparison. ; Detects compare operation in progress. ; Detects the ADCCMP flag, then ; Subtracts (8/64) x VDD when the flag is set to 0. ; Adds (4/64) x VDD. ; Starts comparison. ; Detects compare operation in progress. ; Detects the ADCCMP flag, then ; Subtracts (16/64) x VDD when the flag is set to 0. ; Adds (8/64) x VDD. ; Starts comparison. ; Detects compare operation in progress. ; Detects the ADCCMP flag, then ; Subtracts (32/64) x VDD when the flag is set to 0. ; Adds (16/64) x VDD. ; Sets (31.5/64) x VDD as the reference voltage VREF. ; Starts comparison. ; Detects compare operation in progress. 182 PD17068 SKT1 CLR1 SET1 PUT SET1 SKF1 BR SKT1 CLR1 SET1 PUT SET1 SKF1 BR SKT1 CLR1 END: (b) Method with a smaller number of program steps INIT: WORKR1 MEM 0.01H WORKR0 MEM 0.00H ; ; ; Sets the ADC0 pin for the A/D converter. START: MOV MOV MOV MOV CLR1 LOOP: RORC RORC SKF1 BR PUT SET1 SKF1 BR SKT1 BR AAA: OR DBF1, WORK1 WORK1 WORK0 CY END ADCR, DBF ADCEN ADCEN $-1 ADCCMP BBB ; Sets (31.5/64) x VDD as the reference voltage VREF. ; Starts comparison. ; Detects compare operation in progress. DBF1, #0010B DBF0, #0000B WORKR1, #0110B WORKR0, #0000B CY ADCCMP ADCR2 ADCR1 ADCR, DBF ADCEN ADCEN $-1 ADCCMP ADCR1 ADCR0 ADCR, DBF ADCEN ADCEN $-1 ADCCMP ADCR1 ; Detects the ADCCMP flag, then ; Subtracts (1/64) x VDD when the flag is set to 0. ; Starts comparison. ; Detects compare operation in progress. ; Detects the ADCCMP flag, then ; Subtracts (2/64) x VDD when the flag is set to 0. ; Adds (1/64) x VDD. ; Starts comparison. ; Detects compare operation in progress. ; Detects the ADCCMP flag, then ; Subtracts (4/64) x VDD when the flag is set to 0. ; Adds (2/64) x VDD. INITFLG NOT ADCCH3, NOT ADCCH2, NOT ADCCH1, NOT ADCCH0 183 PD17068 OR BR BBB: EOR EOR BR END: 13.7 NOTES ON USING A/D CONVERTER DBF1, WORKR1 DBF0, WORKR0 LOOP DBF0, WORK0 LOOP When the P1C0/ADC5 to P1C2/ADC7 pins are used for the A/D converter, the pins need to be set as generalpurpose input ports with the P1CGIO flag. Port 1C is a group I/O, so that the P1C3 pin can be used only as a general-purpose input port when the A/D converter is used. 13.8 13.8.1 STATES UPON RESET Power-On Reset The P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN, P0D0/ADC1/XTOUT pins, and P1C2/ADC7 to P1C0/ADC5 pins are set as general-purpose input ports. 13.8.2 Clock Stop The P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN, P0D0/ADC1/XTOUT pins, and P1C2/ADC7 to P1C0/ADC5 pins are set as general-purpose input ports. 13.8.3 CE Reset The P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN, P0D0/ADC1/XTOUT pins, and P1C2/ADC7 to P1C0/ADC5 pins are set as general-purpose input ports. 184 PD17068 14. D/A CONVERTER (PWM METHOD) 14.1 OUTLINE OF D/A CONVERTER Fig. 14-1 outlines the D/A converter. The D/A converter outputs a signal according to the pulse width modulation (PWM) method, which allows a variable duty cycle. By attaching an external low-pass filter, a digital signal can be converted to an analog signal. A signal with a variable duty cycle is output on each pin independently. The output frequency is 1953 Hz, and the duty cycle can be changed in 256 steps. Fig. 14-1 Schematic Diagram of D/A Converter Duty cycle setting block DBF Output switching block P2C0/PWM0 8 PWM data register (PWMR0, 3, 6) Clock generation block fPWM0 fPWM1 fPWM2 P2C3/PWM3 Match Comparator P2B2/PWM6 0 detected 8-bit counter DBF Output switching block P2C1/PWM1 8 PWM data register (PWMR1, 4, 7) P2B0/PWM4 Match Comparator P2B3/PWM7 0 detected 8-bit counter DBF Output switching block P2C2/PWM2 8 PWM data register (PWMR2, 5, 8) P2B1/PWM5 Match Comparator P2A0/PWM8 0 detected 8-bit counter 185 PD17068 14.2 OUTPUT SWITCHING BLOCK According to the PWM0SEL-PWM8SEL flags of PWM mode select registers 1 to 3, the output switching block determines whether each output pin of the D/A converter is to be used for the D/A converter or as a generalpurpose output port. Fig. 14-2 shows the configuration of the output switching block. Fig. 14-3 through Fig. 14-5 show the formats and functions of PWM mode select registers 1 to 3. Whether to use a pin for the D/A converter or as a general-purpose output port can be set independently of other pins. Each output pin is an N-ch open drain output, so that a pull-up resistor is externally required. Fig. 14-2 Configuration of Output Switching Block PWM0SEL-PWM8SEL flags Each output pin 1 0 Output latch Comparator output Fig. 14-3 Format of PWM Mode Select Register 3 Flag symbol Register b3 b2 b1 b0 P W M 8 S E L Address Read/write PWM mode select register 3 0 0 0 03H R/W Sets the function of P2A0/PWM8 pin. 0 1 General-purpose output port D/A converter Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 0 Hold 186 PD17068 Fig. 14-4 Format of PWM Mode Select Register 2 Flag symbol Register b3 P W M 7 S E L b2 P W M 6 S E L b1 P W M 5 S E L b0 P W M 4 S E L Address Read/write PWM mode select register 2 04H R/W Sets the function of P2B0/PWM4 pin. 0 1 General-purpose output port D/A converter Sets the function of P2B1/PWM5 pin. 0 1 General-purpose output port D/A converter Sets the function of P2B2/PWM6 pin. 0 1 General-purpose output port D/A converter Sets the function of P2B3/PWM7 pin. 0 1 General-purpose output port D/A converter Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 Hold 187 PD17068 Fig. 14-5 Format of PWM Mode Select Register 1 Flag symbol Register b3 P W M 3 S E L b2 P W M 2 S E L b1 P W M 1 S E L b0 P W M 0 S E L Address Read/write PWM mode select register 1 05H R/W Sets the function of P2C0/PWM0 pin. 0 1 General-purpose output port D/A converter Sets the function of P2C1/PWM1 pin. 0 1 General-purpose output port D/A converter Sets the function of P2C2/PWM2 pin. 0 1 General-purpose output port D/A converter Sets the function of P2C3/PWM3 pin. 0 1 General-purpose output port D/A converter Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 Hold 14.3 DUTY CYCLE SETTING BLOCK The duty cycle setting block compares the value set in each PWM data register (PWMR0-PWMR8) with the count value of each 8-bit counter with the timing of each basic clock (fPWM0, fPWM1, fPWM2). The block outputs the low level when a match with the value of a PWM data register is found. When the counter value reaches 0, the block outputs the high level with the timing of a basic clock. Let x be the value set in a PWM data register. Then, the duty cycle is as follows: Duty cycle: D = x 256 x 100% A basic clock of 500 kHz is used, so that the frequency and period of an output signal are as follows: Frequency: f = 500 kHz . = 1.953 kHz . 256 188 PD17068 Period: T = 256 500 kHz = 512 s For each pin, a different value can be set in each PWM data register through the data buffer (DBF). This means that a signal with an independent duty cycle can be output on each pin. Fig. 14-6 shows the format of the PWM data registers. Fig. 14-6 Format of PWM Data Registers Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET 8 PUT Peripheral register Register PWM0 data register PWM1 data register PWM2 data register PWM3 data register PWM4 data register PWM5 data register PWM6 data register PWM7 data register PWM8 data register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5 PWMR6 PWMR7 PWMR8 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H DBF0 Valid data Sets the PWM output duty cycle for each pin. 0 Duty ratio : D = x x 256 500 256 x 100% Frequency : f = kHz = 1953 Hz 255 189 PD17068 14.4 CLOCK GENERATION BLOCK The clock generation block outputs the basic clocks (fPWM0, fPWM1, fPWM2) used to set the duty cycle of each output signal. The output frequency is 500 kHz for all of fPWM0, fPWM1, fPWM2. Fig. 14-7 shows the phase differences among the clocks. Fig. 14-7 Phase Differences among Basic Clocks fPWM0 fPWM1 fPWM2 500 ns 500 ns 2 s 500 ns 500 ns 14.5 OUTPUT WAVEFORMS OF D/A CONVERTER The relationships between duty cycles and output waveforms are shown in (1). The output waveform on each pin is shown in (2) below. A phase difference results because of a different basic clock supplied. (1) Duty cycles and output waveforms x=0 x=1 x=2 2 s 2 s 2 s x = 255 512 s 190 PD17068 (2) Output waveform on each pin PWM0, PWM1, PWM6 (x = 1) PWM1, PWM4, PWM7 (x = 1) PWM2, PWM5, PWM8 (x = 1) 1 s 500 ns 512 s 14.6 NOTES ON USING D/A CONVERTER (1) After turning on the power, perform initial PWM output setting according to the procedure below. The PWM data registers are undefined when the power is turned on, so that this procedure is required to set desired data beforehand. # $ Set desired values in the PWM data registers. Set the PWMnSEL flags. (2) Never rewrite the data set in a PWM data register during PWM operation. This is because an output signal with a correct duty cycle cannot be obtained during one period (512 s). 14.7 14.7.1 STATES UPON RESET Power-On Reset The P2C0/PWM0 to P2A0/PWM8 pins are set as general-purpose output ports. All values output at this time are undefined. The value of each PWM data register is undefined. 14.7.2 Clock Stop The P2C0/PWM0 to P2A0/PWM8 pins are set as general-purpose output ports. All values output at this time are the previous latch values. The previous value of each PWM data register is preserved. 14.7.3 CE Reset The P2C0/PWM0 to P2A0/PWM8 pins preserve the previous output states. This means that those pins that are used for the D/A converter preserve the PWM output states. 14.7.4 Halt State The P2C0/PWM0 to P2A0/PWM8 pins preserve the previous output states. This means that those pins that are used for the D/A converter preserve the PWM output states. 191 PD17068 15. SERIAL INTERFACE 15.1 GENERAL Fig. 15-1 outlines the serial interface. Table 15-1 shows the serial interface classes and communication modes. As shown in Fig. 15-1, the serial interface consists of two systems: serial interface 0 (SIO0) and serial interface 1 (SIO1). Serial interface 0 and serial interface 1 can be used simultaneously. Serial interface 0 can use a 2-wire system or a 3-wire system. The 2-wire system uses the SDA and SCL pins and the 3-wire system uses the SCK0, SO0, and SI0 pins. With the 2-wire system, I2C bus or serial I/O can be selected as the communication mode. Serial interface 1 can only use a 3-wire system. The pins used are SCK1, SO1, and SI1. The communication mode is serial I/O. Fig. 15-1 Serial Interface SDA/P0A0 SCL/P0A1 SCK0/P0A2 SO0/P0A3 SI0/P0B0 I/O control Presettable shift register 0 Clock control block 8 MHz Interrupt control block IRQSIO0 flag Serial interface 0 SCK1/P2D0 SO1/P2D1 SI1/P2D2 I/O control Presettable shift register 1 Clock control block 8 MHz IRQSIO1 flag Serial interface 1 192 PD17068 Table 15-1 Serial Interface Classes and Communication Modes Channel Serial interface 0 Number of wires 2-wire system Communication mode I 2C bus Pins used P0A0/SDA P0A1/SCL P0A2/SCK0 P0A3/SO0 P0B0/SI0 P2D0/SCK1 P2D1/SO1 P2D2/SI1 Serial I/O 3-wire system Serial I/O Serial interface 1 3-wire system Serial I/O 15.2 15.2.1 SERIAL INTERFACE 0 General Fig. 15-2 outlines serial interface 0. Serial interface 0 can use a 2-wire I2C bus or 2-wire/3-wire serial I/O mode. Fig. 15-2 Serial Interface 0 SIO0CH flag SB flag SIO0MS flag SIO0CK0 and SIO0CK1 flags Wait signal SCL/P0A1 Clock I/O control block SIO0WRQ0 and SIO0WRQ1 flags SIO0NWT flag Clock control block 8 MHz Wait control block SCK0/P0A2 SIO0IMD0 and SIO0IMD1 flags Clock counter SIO0CH flag SB flag SIO0TX flag SIO0SF8 and SIO0SF9 flags Counts 8 and 9 SBSTT and SBBSY flags Start/stop detection block Interrupt control block SDA/P0A0 Presettable shift register 0 SO0/P0A3 Data I/O control block OUT (SIO0SFR) Serial data IN SI0/P0B0 ACK Acknowledge control block SBACK flag 193 PD17068 Remarks 1. SIO0CH (bit 3 of serial I/O-0 mode selection register: see Fig. 15-3): 2-wire/3-wire system selection 2. SB (bit 2 of serial I/O-0 mode selection register: see Fig. 15-3): I2 C bus/serial I/O selection 3. SIO0MS (bit 1 of serial I/O-0 mode selection register: see Fig. 15-3): Master/slave selection 4. SIO0TX (bit 0 of serial I/O-0 mode selection register: see Fig. 15-3): Receive/transmit selection 5. SIO0CK0 and SIO0CK1 (bits 0 and 1 of serial I/O-0 clock selection register: see Fig. 15-4): Set the internal shift clock frequency. 6. SIO0WRQ0 and SIO0WRQ1 (bits 0 and 1 of serial I/O-0 wait control register: see Fig. 15-7): Set the communication wait condition. 7. SIO0NWT (bit 2 of serial I/O-0 wait control register: communication. 8. SIO0SF8 and SIO0SF9 (bits 3 and 2 of serial I/O-0 status judge register: see Fig. 15-5): Clock counter detection 9. SBSTT and SBBSY (bits 1 and 0 of serial I/O-0 status judge register: see Fig. 15-5): I2C bus start condition, stop condition, and clock counter detection 10. SIO0IMD0 and SIO0IMD1 (bits 0 and 1 of serial I/O-0 interrupt mode register: see Fig. 15-8): Set the interrupt timing. 11. SBACK (bit 3 of serial I/O-0 wait control register: see Fig. 15-7): Acknowledge data read/write 15.2.2 Clock I/O Control Block and Data I/O Control Block see Fig. 15-7): Sets the start of The clock I/O control block and data I/O control block control the serial interface 0 communication mode (I2C bus or serial I/O), the pins used (2-wire system or 3-wire system), and the transmit and receive operations. The SIO0CH and SB flags select the 2-wire/3-wire system and I2C bus/serial I/O, respectively. The SIO0MS flag selects internal clock (master)/external clock (slave) and the SIO0TX flag selects the receive (RX)/transmit (TX) operation. These flags are located in the serial I/O-0 mode selection register. Fig. 15-3 shows the organization and functions of the serial I/O-0 mode selection register. Table 15-2 shows the pin settings. As shown in Table 15-2, to set the pins, the serial interface control flag and the I/O setting flag of each pin, must be manipulated. 194 PD17068 Fig. 15-3 Organization of Serial I/O-0 Mode Selection Register Flag symbol Register b3 S I O 0 C H b2 S B b1 S I O 0 M S b0 S I O 0 T X Address Read/write Serial I/O0 mode selection register 08H R/W Sets the SDA/P0A0 pin (2-wire system) and SO0/P0A3 pin (3-wire system) serial I/O mode. (Receive "RX" and transmit "TX" operation selection) 2-wire system (SDA/P0A0 pin) 0 1 Serial input (Hi-Z) : RX operation Serial output : TX operation 3-wire system (SO0/P0A3 pin) General-purpose port Serial output : TX operation Sets the shift clock to be used. 2 I C bus mode Serial I/O mode External clock input Internal clock output 0 1 Slave operation (external clock input) Master operation (internal clock output) I2C bus or serial I/O mode selection 0 1 Serial I/O mode 2 I C bus mode (At this time, do not set the SIO0CH flag to 1.) 2-wire system or 3-wire system selection 0 1 2-wire system 3-wire system (At this time, do not set the SB flag to 1.) Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 195 PD17068 Table 15-2 Pin Settings by Control Flag Flag S I O 0 C H S B S I Communication O 0 mode M S S I O 0 T X P O A B I O 3 P O A B I O 2 P O A B I O 1 Pin P O A B I O 0 0 P0A0/SDA 1 Output (transmit) 0 0 0 2-wire serial I/O 0 External P0A1/SCL 1 Internal 1 P0A2/SCK0 P0A3/SO0 P0B0/SI0 0 Input (receive) P0A0/SDA 1 Output (transmit) 0 P0A1/SCL 1 Internal (master) P0A2/SCK0 P0A3/SO0 P0B0/SI0 P0A0/SDA P0A1/SCL 0 0 External 1 P0A2/SCK0 0 1 1 0 3-wire serial I/O 0 Internal 1 Generalpurpose port P0A3/SO0 1 Output (transmit) 0 Serial output 1 0 P0B0/SI0 1 1 1 Not to be set. General-purpose output port Serial input 0 1 General-purpose input port General-purpose output port Internal clock 1 0 1 General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port External clock General-purpose output port 0 1 0 Serial output 1 External clock (slave) General-purpose output port Internal clock (master) General-purpose I/O port General-purpose I/O port General-purpose I/O port Serial input General-purpose output port 1 0 Internal clock General-purpose output port 1 0 1 External clock P O B B I O 0 Clock to be used Serial I/O Pin name Pin setting 0 Input (receive) Serial input General-purpose output port Serial output 0 1 2-wire I2C bus 0 External (slave) 196 PD17068 15.2.3 Clock Control Block The clock control block controls the clock generation and clock output timings when the internal clock is used (master operation). The SIO0CK0 and SIO0CK1 flags of the serial I/O-0 clock selection register set the internal clock frequency fsc. Fig. 15-4 shows the organization and functions of the serial I/O-0 clock selection register. The shift clock output from the clock control block is valid only during master operation (SIO0MS flag = 1). For the clock generation timing, see the item for each communication mode. Fig. 15-4 Organization of Serial I/O-0 Clock Selection Register Flag symbol Register b3 b2 b1 S I O 0 C K 1 b0 S I O 0 C K 0 Address Read/write Serial I/O-0 clock selection register 0 0 39H R/W Sets the serial interface 0 internal shift clock frequency fSC. 0 0 1 1 0 1 0 1 100 kHz 50 kHz 500 kHz 1 MHz Fixed to 0. Upon reset Power-on Clock stop CE 0 0 Undefined Hold Hold 15.2.4 Clock Counter and Start/Stop Detection Block The clock counter is a wrap around counter that counts the rising edge of the clock pulses. Whether the internal clock or the external clock is used cannot be judged because the clock counter reads the state of the clock pin directly. The contents of the clock counter can be detected through the SIO0SF8 and SIO0SF9 flags of the serial I/O-0 status judge register, but cannot be read directly by program. The start/stop detection block detects the start and stop conditions when the I2C bus mode is used. The start and stop conditions are detected with the SBSTT and SBBSY flags of the I/O-0 status judge register. Fig. 15-5 shows the organization and functions of the serial I/O-0 status judge register. For clock counter operation and timing chart, see the item for each communication mode. 197 PD17068 Fig. 15-5 Organization of Serial I/O-0 Status Change Register Flag symbol Register b3 S I O 0 S F 8 b2 S I O 0 S F 9 b1 S B S T T b0 S B B S Y Address Read/write Serial I/O0 status judge register 28H R I2C bus mode start/stop condition detection I2C bus mode 0 1 Detect stop condition Hold at "0". Detect start condition Serial I/O mode 2 I C bus mode start condition and clock counter detection I2C bus mode 0 1 Detect falling edge of clock when clock counter reaches "9". Detect start condition Serial I/O mode Hold previous value. Clock counter detection I2C bus mode 0 1 Clock counter "0" or "1" Detect rising edge of clock when clock counter reaches "9". Clock counter "9". Serial I/O mode Clock counter detection 2 I C bus mode Serial I/O mode 0 1 Clock counter "0" or "1" Detect rising edge of clock when clock counter reaches "8". Clock counter "8" Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 198 PD17068 15.2.5 Presettable Shift Register 0 Presettable shift register 0 is an 8-bit shift register for writing serial out data and reading serial in data. It is written and read through a data buffer. Presettable shift register 0 outputs the contents of the most significant bit (MSB) to the serial data I/O pin in synchronization with the falling edge of the shift clock and reads data at the least significant bit (LSB) in synchronization with the rising edge of the shift clock. Fig. 15-6 shows the organization and functions of presettable shift register 0. Fig. 15-6 Organization of Presettable Shift Register 0 Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GETNote 8 PUTNote Peripheral register Register Presettable shift register 0 b7 M S B b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral register L S SIO0SFR B 03H DBF0 Valid data Serial out data write and serial in data read D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial out Serial in Note If a PUT or GET instruction is executed during serial communication, the data may be destroyed. For details, see Section 15.2.10. 199 PD17068 15.2.6 Wait Control Block and Acknowledge Control Block The wait control block controls communication wait and release. The SIO0WRQ0 and SIO0WRQ1 flags (bits 0 and 1 of the serial I/O-0 wait control register) set the wait condition. Serial communication is started by setting (wait release) the SIO0NWT flag (bit 2 of the serial I/O-0 wait control register). The communication state can be detected with the SIO0NWT flag. When "0" is written in the SIO0NWT flag in the wait released state, the wait state is set. This is called "forced wait". The acknowledge control block outputs and detects the acknowledge signal when the I2C bus mode is used. Acknowledge is written and read by the SBACK flag (bit 3 of the serial I/O-0 wait control register). Fig. 15-7 shows the organization and functions of the serial I/O-0 wait control register. 200 PD17068 Fig. 15-7 Organizations of Serial I/O-0 Wait Control Register Flag symbol Register b3 S B A C K b2 S I O 0 N W T b1 S I O 0 W R Q 1 b0 S I O 0 W R Q 0 Address Read/write Serial I/O-0 wait control register 18H R/W Wait condition setting Name 0 0 No wait 2 I C bus mode Serial I/O mode Does not wait. 0 1 Data wait The wait state is set by the falling edge of the shift clock when the clock counter reaches "8". The wait state is set by the falling edge of the shift clock when the clock counter reaches "9". The wait state is set by the rising edge of the shift clock when the clock counter reaches "8". The wait state is set by the rising edge of the shift clock when the clock counter reaches "9". 1 0 Acknowledge wait 1 1 Address wait Falling edge of clock when clock counter reaches "8" after start Not to be set. condition detected. Wait setting and wait state detection When flag written 0 Forced wait Release wait (serial communication start) When flag read Wait according to the condition specified with the SIO0WRQ0 and SIO0WRQ1 flags In serial communication 1 I2C bus mode acknowledge signal setting and detection 2 I C bus mode At reception (SIO0TX = 0) At transmission (SIO0TX = 1) Detect slave acknowledge (acknowledge = "0") Serial I/O mode 0 Output "0" as acknowledge 1 Output "1" as acknowledge Detect slave acknowledge (acknowledge = "1") No operation. Therefore, can be used for other purposes. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 201 PD17068 15.2.7 Interrupt Control Block In the interrupt control block, the serial I/O-0 interrupt mode register specifies the condition at which an interrupt request is issued. When the interrupt request condition is established, the IRQSIO0 flag is set. Change the interrupt condition in the wait state. If the interrupt condition is changed in the wait released state, an interrupt request may be issued at the time the condition is changed. Fig. 15-8 shows the organization and functions of the serial I/O-0 interrupt mode register. Fig. 15-8 Organization of Serial I/O-0 Interrupt Mode Register Flag symbol Register b3 b2 b1 S I O I M D 1 b0 S I O I M D 0 Address Read/write Serial I/O-0 interrupt mode register 0 0 38H R/W Sets the interrupt request condition. 2 I C bus mode Serial I/O mode Rising edge of shift clock when clock counter reaches"7". Note 1 Rising edge of shift clock when clock counter reaches "8". Note 2 0 0 Rising edge of shift clock when clock counter reaches "7". Rising edge of shift clock when clock counter reaches"8". Rising edge of shift clock when clock counter reaches"7" after start condition detected. Note 3 When stop condition detected. Note 4 0 1 1 0 Interrupt request not issued. 1 1 Fixed to 0. Upon reset Power-on Clock stop CE 0 0 Undefined Hold Hold Notes 1. If this mode is set when the clock counter count is "7", an interrupt request is issued. 2. If this mode is set when the clock counter count is "8", an interrupt request is issued. 3. If this mode is set when the SBSTT flag is "1" and the clock counter count is "7", an interrupt request is issued. 4. If this mode is set after the stop condition has been specified, an interrupt request is issued. 202 PD17068 15.2.8 I2C Bus Mode (1) General The I2C bus mode communicates with 2-wires: SCL pin and SDA pin. It has the following features: q Communication can be controlled by start/stop conditions and 9th clock acknowledge. q The communication wait state can be set by externally fixing the clock at a low level by using the N-ch open drain pin. (2) Timing chart Fig. 15-9 is the timing chart. Fig. 15-9 I2C Bus Mode Timing Chart Start condition Shift clock Serial data La 1 D7 2 D6 3 D5 7 D1 8 D0 9 ACK Stop condition Clock counter SIO0NWT 0 1 2 6 7 8 9 1 SIO0SF8 SIO0SF9 SBSTT SBBSY Remarks # Start condition generation by general-purpose I/O port $ Master transmit state setting % Wait release & Wait timing at address wait and data wait setting ( Wait timing at acknowledge wait setting ) Stop condition generation by general-purpose I/O port ), *, + Interrupt request timing 203 PD17068 (3) Clock counter operation The clock counter initial value is "0". Thereafter, the clock counter is incremented each time the rising edge of the clock pin signal is detected. When the clock counter reaches "9", it returns to "1" and continues counting. The clock counter reset conditions are: # $ % & ( Power-on reset Clock-stop instruction execution Start condition detection Communication mode switched from I2C bus mode to 2-wire or 3-wire serial I/O mode CE reset (4) Wait operation and cautions When the wait state is released, serial data is immediately output (at transmit operation) and the serial interface remains in the wait released state until the condition set by the SIO0WRQ0 and SIO0WRQ1 flags is satisfied. When the wait condition is satisfied, the shift clock pin is made low level and operation of the clock counter and presettable shift register 0 is stopped. Note that if data is written into presettable shift register 0 while the serial interface is in the released state and the shift clock pin is low level, the data may not be written correctly. If forced wait is specified in the wait released state, the forced wait state is set at the falling edge of the next clock pulse after "0" is written in the SIO0NWT flag. The wait released state is not changed even if wait release is specified again in that state. Note that when forced wait is specified in the wait state, one shift clock is output. When using the I2C bus mode, do not set the data wait condition (SIO0WRQ0 = 1, SIO0WRQ1 = 0) consecutively. This is because when the data wait condition is set twice in succession to release the wait state, the wait state will be immediately set when it is released for the second time. When the shift clock output pin is externally forced to low level while it is at high level during master operation (this is called wait request from a slave), master operation is set to the wait state. In this case, operation restarts at the time the slave wait request is cleared. (5) Interrupt request timing The interrupt request timing can be selected with the SIO0IMD0 and SIO0IMD1 flags. 204 PD17068 (6) Acknowledge block and its operation The acknowledge block operates only when the I2 C bus mode is used. It is used in receive operation acknowledge signal output and transmit operation acknowledge signal detection. During the receive operation, the contents of the SBACK flag are output from the serial data pin at the falling edge of the shift clock when the clock counter reaches "8". During the receive operation, once data is set in the SBACK flag, that value is held. During the transmit operation, the state of the serial data pin is read at the SBACK flag at the rising edge of the shift clock when the clock counter reaches "9". Fig. 15-10 shows the acknowledge output and input operations. During the receive operation, set acknowledge (SBACK flag setting) simultaneously with release of the wait state (SIO0NWT flag setting). This is because the SBACK and SIO0NWT flags are included in the same register. As a result, if only the SBACK flag is set, the SIO0NWT flag is also set. If the serial interface is in the wait state, the wait state is released in the wait state and one shift clock is output. Fig. 15-10 Acknowledge Output and Input Operations q Receive operation Shift clock 7 8 9 Data Hi-Z (D1) Data input Hi-Z (D0) SBACK output Hi-Z Acknowledge output Wait release must be set at the same time. q Transmit operation Shift clock 7 8 9 Data D1 output Data output D0 output Receiving side ACK Acknowledge input 205 PD17068 (7) Shift clock generation timing in I2C bus mode (a) When the initial state is released "Initial state" refers to the time that I2C bus method master operation is selected. While the serial interface is in the wait state, low level is output from the shift clock pin. Fig. 15-11 Shift Clock Generation Timing in I2 C Bus Mode (1/5) Shift clock 1:1 Wait state 1/fSC Initialization Wait release (b) When wait operation is performed # When the interface enters the wait state when the condition specified with the SIO0WRQ0 and SIO0WRQ1 flags is satisfied (normal operation) Fig. 15-11 Shift Clock Generation Timing in I2 C Bus Mode (2/5) Shift clock Wait released state Wait time 1/fSC Wait caused by SIO0WRQ1 and SIO0WRQ0 Wait release $ When forced wait is set in the wait state Nothing changes. 206 PD17068 % When forced wait is set in the wait released state The wait state is set at the falling edge of the next clock after forced wait is set. However, operation of the clock counter and presettable shift register 0 is stopped at the time force wait is set. When forced wait is set when the clock pin is low level, the clock counter and presettable shift register 0 operate for one clock. Fig. 15-11 Shift Clock Generation Timing in I2 C Bus Mode (3/5) Shift clock Wait released state Wait hold Wait time 1/fSC Forced wait caused by SIO0NWT Shift clock Wait hold Wait release Wait time 1/fSC Forced wait caused by SIO0NWT Wait release & When wait release is specified in wait released state Nothing changes. ( When a slave issued a wait request in wait released state The clock is output at the timing shown in Fig. 15-11 (4/5) after the slave wait request is cleared. The values of T1 and T2 in the table are: fsc 50 kHz 100 kHz 500 kHz 1 MHz T1 0 to 10 s 0 to 5 s 0 to 1 s 0 to 687.5 ns T2 1 to 10 s 1 to 5 s 0.5 to 1 s 187.5 to 500 ns Fig. 15-11 Shift Clock Generation Timing in I2 C Bus Mode (4/5) q If wait request is issued when the SCL pin is at low level Shift clock Wait release state Slave wait request T1 T2 1/fSC Slave wait request clear 207 PD17068 Remark If the slave wait request is cleared before the next rising edge of the SCL pin signal, wait is not recognized and operation continues. q If wait request is issued when the SCL pin is at high level Shift clock Slave wait request T1 T2 1/fSC Slave wait request clear (c) Slave (external clock) operation At the first slave operation setting after the power supply voltage VDD is turned on, the SCL pin output is undefined. At this time, if the SCL pin is externally set to low level, it outputs low level until the next time the wait state is released. Fig. 15-11 Shift Clock Generation Timing in I2 C Bus Mode (5/5) Shift clock I/O port Wait time (originally Hi-Z) Wait release time Slave set Wait release (8) Start/stop conditions and SBSTT and SBBSY flags operation Fig. 15-12 shows the fetch timing of the start and stop conditions. To fetch the start and stop conditions correctly, the shift clock must satisfy the states indicated in the figure for at least 1 s (T3 and T4) before and after the edges of the serial data. When this condition is satisfied, the SBSTT and SBBSY flags change 2 s after the edges. The SBSTT and SBBSY flags operate only when the I2C bus mode is used. The communication state of the other station can be detected by detecting these flags. These flags operate without regard to master, slave, receiving, transmitting, waiting, or wait released. For the serial I/O mode, "0" is held. For a description of SBSTT flag and SBBSY flag operation, see Fig. 15-9. 208 PD17068 Fig. 15-12 Start/Stop Conditions Fetch Timing (a) Start condition fetch timing H Shift clock pin L H Serial data pin SBSTT, SBBSY L H L T3 T4 2 s Note T3 and T4 must be at least 1 s. (b) Stop condition fetch timing H Shift clock pin L H Serial data pin L H SBBSY L T3 T4 2 s Note T3 and T4 must be at least 1 s. Remark Fig. 15-12 (a) and (b) indicate the timings with a clock frequency of 8 MHz. 209 PD17068 15.2.9 Serial I/O Mode (1) General In the serial I/O mode, communication is performed with the 2-wire system, which uses the SCL and SDA pins, on with the 3-wire system, which uses the SCK0, SO0, and SI0 pins. (2) Timing chart Fig. 15-13 is the serial I/O mode timing chart. Fig. 15-13 Serial I/O Mode Timing Chart Shift clock Serial data La 1 D7 2 D6 3 D5 7 D1 8 D0 9 d7 1 D7 Clock counter SIO0NWT SIO0SF8 SIO0SF9 SBSTT SBBSY 0 1 2 6 7 8 9 1 "0" "0" Note Note SIO0SF8 and SIO0SF9 are also reset when the I/O-0 wait control register is written. Remarks # Master transmit state setting $ Wait release % Wait timing at address wait and data wait setting & Wait timing at acknowledge wait setting (, ) Interrupt timing 210 PD17068 (3) Clock counter operation The clock counter initial value is "0". Thereafter, the clock counter is incremented each time the rising edge of the clock pin signal is detected. When the clock counter reaches "9", it returns to "1" and continues counting. The clock counter reset conditions are: # $ % & ( Power-on reset Clock-stop instruction execution Data written to serial I/O-0 wait control register Communication mode switched from 2-wire or 3-wire serial I/O mode to I2C bus mode CE reset (4) Wait operation and cautions If the wait state is released, serial data is output (at transmit operation) at the falling edge of the next clock and the serial interface remains in the wait released state until the condition set with the SIO0WRQ0 and SIO0WRQ1 flag is satisfied. When the wait condition is satisfied, the shift clock pin is made high level and operation of the clock counter and presettable shift register 0 is stopped. Note that if data is written and read to and from presettable shift register 0 while the serial interface is in the wait released state and the shift clock pin is high level, the data will not be written correctly. If data is written into presettable shift register 0 while the serial interface is in the wait released state and the shift clock pin is low level, the contents of MSB is output from the serial data output pin when the PUT instruction is executed. If forced wait is set in the wait released state, the wait state is set as soon as "0" is written in the SIO0NWT flag. Note that if wait release is set again in the wait released state, the clock counter will be reset. (5) Interrupt request timing The interrupt request timing can be selected with the SIO0IMD0 and SIO0IMD1 flags. See Section 15.2.7. (6) Acknowledge block and its operation The acknowledge block operates only when the I2 C bus mode is used. (7) Serial I/O shift clock generation timing (a) When the initial state is released "Initial state" refers to the time when serial I/O internal clock operation is selected. During the wait state, high level is output from the shift clock pin. 211 PD17068 Fig. 15-14 Shift Clock Generation Timing in Serial I/O Mode (1/4) Shift clock 1:1 Wait state 1/fSC Initialization Wait release (b) When wait operation is performed # When the interface enters the wait state when the condition specified with the SIO0WRQ0 and SIO0WRQ1 flags is satisfied (normal operation) Fig. 15-14 Shift Clock Generation Timing in Serial I/O Mode (2/4) Shift clock Wait released state Wait state 1/fSC Wait caused by SIO0WRQ1 and SIO0WRQ0 Wait release $ When forced wait is set in the wait state Fig. 15-14 Shift Clock Generation Timing in Serial I/O Mode (3/4) Shift clock Wait time Wait time Forced wait by SIO0NWT 212 PD17068 % When forced wait is set in the wait released state After forced wait release, the clock pulses are output at the specified period after the remaining clock pulses are output. T5 is equal to T6. However, when a clock faster than the shift clock is selected, T5 does not equal T6 and becomes 0 T6 500 ns. Fig. 15-14 Shift Clock Generation Timing in Serial I/O Mode (4/4) Falling edge of clock when there was no wait request Shift clock Wait released state T5 Wait time T6 1/fSC Forced wait by SIO0NWT Wait release Rising edge of clock when there was no wait request Shift clock Wait released state T5 T6 1/fSC Wait time Forced wait by SIO0NWT Wait release & When wait is released in the wait released state The clock output waveform does not change. Note that the clock counter is reset. (8) SBSTT and SBBSY flags operation The SBSTT and SBBSY flags operate only when the I2C bus mode is used. For the serial I/O mode, these flags are held at "0". 213 PD17068 15.2.10 Data Write and Read Cautions Data is written to presettable shift register 0 with the "PUT SIO0SFR, DBF" instruction. Data is read with the "GET DBF, SIO0SFR" instruction. Write and read data in the wait state. If data is written and read in the wait released state, the correct data may not be written and read, depending on the state of the shift clock pin. The data write and read timing and cautions are given below. Table 15-3 Presettable Shift Register 0 Data Read and Write Operations and Cautions I2C bus mode State at PUT/ GET execution Wait state Read (GET) State of shift clock pin q Fixed at low level in the I2C bus mode q Fixed at high level in the serial I/O mode Serial I/O mode Normal read Normal read Write (PUT) Normal write The contents of the MSB is output the next time the wait state is released. (At transmit operation) (At transmit operation) H Clock L 1 Data 0 PUT SIO0SFR, DBF Wait release MSB Normal write The contents of the MSB is output at the falling edge of the shift clock pin signal while the wait state is released next time. H Clock L 1 Data 0 PUT SIO0SFR, DBF Wait release MSB Wait released state Read (GET) High level Low level Normal read Normal read Normal write The contents of the MSB is output when the clock falls. The clock counter is not reset. H Clock L 1 Data 0 PUT SIO0SFR, DBF MSB Normal read Normal read Normal write The contents of the MSB is output when the clock falls. The clock counter is not reset. H Clock L 1 Data 0 PUT SIO0SFR, DBF MSB Write (PUT) High level Low level Not written normally. The contents of SIO0SFR are destroyed. Not written normally. The contents of SIO0SFR are destroyed. 214 PD17068 15.2.11 Serial Interface 0 Operation Tables 15-4 through 15-6 outline operation for each communication mode. Table 15-4 I2C Bus Mode Operation Operation mode Slave operation (SIO0MS = 0) Item State of each pin SDA/P0A0 Receive (SIO0TX = 0) When POABI00 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port and outputs the contents of the output latch. I2C bus mode Master operation (SIO0MS = 1) Receive (SIO0TX = 0) When P0ABIO0 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port and outputs the contents of the output latch. Transit (SIO0TX = 1) Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO0. Transit (SIO0TX = 1) Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO0. SCL/P0A1 When P0ABIO0 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port and outputs the contents of the output latch. Outputs the internal clock regardless of P0ABIO1. Clock counter Presettable Output shift register 0 operation Incremented at the rising edge of the SCL pin signal. Not output Shifts and outputs the data from the MSB each time the SCL pin signal falls. Not output Shifts and outputs the data from the MSB each time the SCL pin signal falls. Input Wait operation Waiting Shifts and inputs the data from the LSB each time the SCL pin signal rises. Outputs low level from the SCL pin. SDA pin: Floating SCL pin: Floating and waiting for external clock input SDA pin: Floating and waiting for external data ACK output at the falling edge of the 8th clock. Outputs low level from the SCL pin. SDA pin: State held SCL pin: Floating and waiting for external clock input SDA pin: Outputs data each time the SCL pin signal falls. ACK fetched at the rising edge of the 9th clock Outputs low level from the SCL pin. SDA pin: Floating SCL pin: Outputs the internal clock. SDA pin: Floating and waiting for external data Outputs low level from the SCL pin. SDA pin: State held SCL pin: Outputs the internal clock. SDA pin: Outputs data each time the SCL pin signal falls. Wait released Acknowledge ACK output at the falling edge of the 8th clock. ACK fetched at the rising edge of the 9th clock. 215 PD17068 Table 15-5 2-wire Serial I/O Operation Operation mode 2-wire serial I/O mode Slave operation (SIO0MS = 0) Master operation (SIO0MS = 1) Receive (SIO0TX = 0) When P0ABIO0 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port and outputs the contents of the output latch. Transit (SIO0TX = 1) Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO0. Item State of each pin SDA/P0A0 Receive (SIO0TX = 0) When P0ABIO0 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port. Outputs the contents of the output latch. Transit (SIO0TX = 1) Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO0. SCL/P0A1 When P0ABIO0 = 0, is floating and waiting for external data input When P0ABIO0 = 1, works as a generalpurpose output port. Outputs the contents of the output latch. Outputs the internal clock regardless of P0ABIO1. Clock counter Presettable Output shift register 0 operation Incremented at the rising edge of the SCL pin signal. Not output Shifts and outputs the data from the MSB each time the SCL pin signal falls. Not output Shifts and outputs the data from the MSB each time the SCL pin signal falls. Input Wait operation Waiting Shifts and inputs the data from the LSB each time the SCL pin signal rises. SCL pin: Floating SDA pin: Floating SCL pin: Floating and waiting for external clock input SDA pin: Floating and waiting for external data SCL pin: Floating SDA pin: State held SCL pin: Floating and waiting for external clock input SDA pin: Outputs data each time the SCL pin signal falls. SCL pin: Floating SDA pin: Floating SCL pin: Outputs the internal clock. SDA pin: Floating and waiting for external data SCL pin: Floating SDA pin: State held SCL pin: Outputs the internal clock. SDA pin: Outputs data each time the SCL pin signal falls. Wait released 216 PD17068 Table 15-6 3-wire Serial I/O Operation Operation mode 3-wire serial I/O mode Slave operation (SIO0MS = 0) Master operation (SIO0MS = 1) Receive (SIO0TX = 0) Transit (SIO0TX = 1) Item State of each pin SCK0/P0A2 Receive (SIO0TX = 0) Transit (SIO0TX = 1) When P0ABIO2 = 0, is floating and waiting for external data input When P0ABIO2 = 1, works as a generalpurpose output port. Outputs the contents of the output latch. When P0ABIO3 = 0, works as a generalpurpose input port and is floating When P0ABIO3 = 1, works as a generalpurpose output port and outputs the contents of the output latch. Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO3. Outputs the internal clock regardless of P0ABIO2. SO0/P0A3 When P0ABIO3 = 0, works as a generalpurpose input port and is floating When P0ABIO3 = 1, works as a generalpurpose output port and outputs the contents of the output latch. Outputs the contents of SIO0SFR at the falling edge of the external clock regardless of P0ABIO3. SI0/P0B0 When P0BBIO0 = 0, is floating and waiting for external data input When P0BBIO0 = 1, works as a generalpurpose output port. Outputs the contents of the output latch. Incremented at the rising edge of the SCK0 pin signal. Not output Shifts and outputs the Not output data from the MSB each time the SCK0 pin signal falls. Shifts and outputs the data from the MSB each time the SCK0 pin signal falls. Clock counter Presettable Output shift register 0 operation Input Wait operation Waiting Shifts and inputs the data from the LSB each time the SCK0 pin signal rises. SCK0 pin: Floating SO0 pin: Generalpurpose port SI0 pin: Floating SCK0 pin: Floating SO0 pin: State held SI0 pin: Floating SCK0 pin: High level output SO0 pin: Generalpurpose port SI0 pin: Floating SCK0 pin: Outputs the internal clock. SO0 pin: Generalpurpose port SI0 pin: Floating and waiting for external data SCK0 pin: High level output SO0 pin: State held SI0 pin: Floating Wait released SCK0 pin: Floating and waiting for external clock input SO0 pin: Generalpurpose port SI0 pin: Floating and waiting for external SCK0 pin: Floating and waiting for external clock input SO0 pin: Data output SI0 pin: Floating and waiting for external data SCK0 pin: Outputs the internal clock. SO0 pin: Data output SI0 pin: Floating and waiting for external data 217 PD17068 15.2.12 State When Serial Interface 0 Is Reset (1) Power-on reset All the pins are set to general-purpose input ports. The contents of presettable shift register 0 are undefined. (2) Clock-stop All the pins are set to general-purpose input ports. The contents of presettable shift register 0 retain their previous value. (3) Halt All the terminals remain in their set states. The internal clock stops output when a HALT instruction is executed. The external clock operates. 218 PD17068 15.3 15.3.1 SERIAL INTERFACE 1 General Fig. 15-15 outlines serial interface 1. Serial interface 1 uses the 3-wire serial I/O mode. Fig. 15-15 Serial Interface 1 SIO1CK0 and SIO1CK1 flags Wait signal Clock I/O control block SCK1/P2D0 SIO1TS flag Clock control block 8 MHz Wait control block Clock counter Count value 8 SIO1HIZ flag IRQSIO1 flag Presettable shift register 1 SO1/P2D1 Data I/O control block SI1/P2D2 OUT (SIO1SFR) IN Remarks 1. SIO1CK0 and SIO1CK1 (bits 0 and 1 of the serial I/O-1 mode selection register: see Fig. 15-16) sets the shift clock. 2. SIO1TS (bit 3 of the serial I/O-1 mode selection register: see Fig. 15-16) selects communication operation start/stop. 3. SIO1HIZ (bit 2 of the serial I/O-1 mode selection register: see Fig. 15-16) selects the function of the SO1/P2D1 pins. 15.3.2 Clock I/O Control Block and Data I/O Control Block The clock I/O control block and data I/O control block control the serial interface 1 transmit and receive operations and select the shift clock. The SIO1CK0 and SIO1CK1 flags select internal clock (master) or external clock (slave) operation. The SIO1HIZ flag selects if the SO1 pin is used as serial data output. The flags that control the clock I/O control block and data I/O control block are located in the serial I/O-1 mode selection register. Fig. 15-16 shows the organization and functions of the serial I/O-1 mode selection register. Table 15-7 shows the setting state of each pin. As shown in Table 15-7, to set each pin, the serial interface control flag and the I/O setting flag of each pin must be manipulated. 219 PD17068 Fig. 15-16 Configuration of Serial I/O-1 Mode Selection Register Flag symbol Register b3 S I O 1 T S b2 S I O 1 H I Z b1 S I O 1 C K 1 b0 S I O 1 C K 0 Address Read/write Serial I/O-1 mode selection register 1CH R/W Selects the serial interface 1 shift clock. 0 0 1 1 0 1 0 1 External clock input 100 kHz 500 kHz 1 MHz Selects the function of the P2D1/SO1 pins. 0 1 General-purpose I/O port Serial data output pin Selects serial communication operation start/stop. 0 1 Operation stop (wait state) Operation start Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 15.3.3 Clock Counter The clock counter is a wrap-around counter that counts the rising edge of the clock pulses. The clock counter reads the state of the clock pin directly. Therefore, whether the clock is internal clock or external clock cannot be judged. The contents of the clock counter cannot be directly read by program. 220 PD17068 Table 15-7 Setting of Each Pin by Control Flag Flag S I O Communication 1 mode H I Z S I O 1 C K 1 S I O 1 C K 0 P 2 D B I O 2 P 2 D B I O 1 P 2 D B I O 0 Pin SIO1 pin setting Clock setting Pin name Pin setting Waiting 0 0 0 External clock Waiting 1 SCK1/P2D0 0 3-wire serial I/O 1 1 Generalpurpose port SO1/P2D1 0 1 Serial output 1 0 SI1/P2D2 1 1 0 1 0 1 Internal clock 1 0 : General-purpose input port Wait released : External clock input wait : General-purpose output port Wait released : General-purpose output port Waiting : Outputs high level. Wait released : Internal clock output General-purpose input port General-purpose output port Waiting : Outputs high level. Wait released : Serial data output Serial data input General-purpose output port 0 221 PD17068 15.3.4 Presettable Shift Register 1 Presettable shift register 1 is an 8-bit shift register for writing serial out data and reading serial in data. Presettable shift register 1 writes and reads data through a data buffer. Presettable shift register 1 outputs (at transmit operation) the contents of the most significant bit (MSB) to the serial data I/O pin in synchronization with the falling edge of the shift clock and reads data at the least significant bit (LSB) in synchronization with the rising edge of the shift clock. Fig. 15-17 shows the organization and functions of presettable shift register 1. Fig. 15-17 Configuration of Presettable Shift Register 1 Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET Note 8 PUT Note Peripheral register Register Presettable shift register 1 b7 M S B b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral register L S SIO1SFR B 07H DBF0 Valid data Serial out data write and serial in data read D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial out Serial in Note If a PUT or GET instruction is executed during serial communications, the data may be destroyed. For details, see Section 15.3.7. 15.3.5 Wait Control Block The wait control block controls communication wait and its release. Serial communication is started by setting wait release at the SIO1TS flag of the serial I/O-1 mode selection register. Then, wait is released. Wait is set again 8 clocks after communication started. The communication state can be sensed with the SIO1TS flag. In short, the communication state can be sensed by detecting the state of the SIO1TS flag after it is set to "1". When "0" is written in the SIO1TS flag in the wait released state, the wait state is set. This is called "forced wait". For the organization and functions of the serial I/O-1 mode selection register, see Fig. 15-16. 222 PD17068 15.3.6 Serial Interface 1 Operation (1) Timing chart Fig. 15-18 shows the timing chart. Fig. 15-18 Serial Interface 1 Timing Chart t Shift clock Serial data La 1 D7 2 D6 3 D5 7 D1 8 D0 1 D7 Clock counter SIO1TS 0 1 2 6 7 Remarks # Master transmit state setting (SIO1HIZ=1) $ Wait release % Wait timing & Interrupt timing transfer. The time until high level is output is (when the main clock is 8 MHz for both Caution As shown in Fig. 15-18, serial data output pin SO1 outputs high level after the end of serial data # $ # and $): When internal clock selected as shift clock source t = 312.5 ns When external clock selected as shift clock source 312.5 t 125 ns (2) Clock counter operation The clock counter initial value is "0", and is incremented each time the rising edge of the clock pin signal is detected thereafter. When the clock counter reaches "8", it returns to "1" and continues counting. The clock counter reset conditions are: # $ % & ( Power-on reset Clock-stop instruction execution "0" was written in the SIO1TS flag Rising edge of shift clock when clock counter reaches "8" in the wait released state CE reset 223 PD17068 (3) Wait operation and cautions When the wait state is released, serial data is output (at transmit operation) at the falling edge of the next clock and serial interface 1 remains in the wait released state for 8 clocks. After 8 clocks are output, the shift clock pin is made high level and clock counter and presettable shift register 1 operation stops. Note that if presettable shift register 1 is written or read when the serial interface is in the wait released state and the shift clock pin is high level, the data may not be set correctly. If presettable shift register 1 is written or read when the serial interface is in the wait released state and the shift clock pin is low level, the contents of the MSB are output from the serial data output pin when a "PUT" instruction is executed. If forced wait is set in the wait released state, serial interface 1 enters the wait state as soon as "0" is written in the SIO1TS flag. Note that if wait release is set again in the wait released state, the clock counter is reset. (4) Interrupt request timing An interrupt request is issued when 8 clocks are transmitted (received). (5) Shift clock generation timing (a) When the initial state is released "Initial state" refers to the time when internal clock operation is selected and the P2D0/SCK1 pin is set to high level. During the wait state, high level is output from the shift clock pin. Wait can be released and the clock can be selected simultaneously. Fig. 15-19 Serial Interface 1 Shift Clock Generation Timing (1/4) Shift clock 1:1 Wait state tX 1/fSC Initialization Wait release 224 PD17068 (b) When wait operation is performed # When wait is set at 8th clock (normal operation) Fig. 15-19 Serial Interface 1 Shift Clock Generation Timing (2/4) Shift clock Wait released state Wait state tX 1/fSC $ When forced wait is set in wait state Wait Wait release Fig. 15-19 Serial Interface 1 Shift Clock Generation Timing (3/4) Shift clock Wait time Wait time Forced wait by SIO1TS % When forced wait is set in wait released state Fig. 15-19 Serial Interface 1 Shift Clock Generation Timing (4/4) Shift clock Wait released state Wait state tX 1/fSC Forced wait by SIO1TS Shift clock Wait released state Wait state Wait release tX 1/fSC Forced wait by SIO1TS Wait state Caution The value of tX in Fig. 15-19 is normally 187.5 ns. However, when 1 MHz is selected as the serial clock, tX becomes 687.5 ns (187.5 + 500 ns). & When wait release is specified in wait released state The clock output waveform does not change. The clock counter is not reset either. However, do not change the clock frequency in the wait released state. 225 PD17068 15.3.7 Data Write and Data Read Cautions Data is written to presettable shift register 1 with the "PUT SIO1SFR, DBF" instruction. Data is read from presettable shift register 1 with the "GET DBF, SIO1SFR" instruction. Write and read data in the wait state. In the wait released state, the data may not be set and read correctly, depending on the state of the shift clock pin. The data write and read timing and cautions are given below. Table 15-8 Presettable Shift Register 1 Data Read and Data Write Operations and Cautions State at PUT/GET execution Wait state Read (GET) Write (PUT) State of shift clock pin Operation of presettable shift register 1 Normal read q Floating when an external clock is used q High level output when the internal clock is used SIO1SFR are destroyed.) Normal write The contents of the MSB is output the next time the wait state is released. (At transmit operation) (If the clock pin is low level in the wait state when an external clock is used, data is not written normally. The contents of Clock Data MSB PUT SIO1SFR, DBF Wait released state Read (GET) High level Low level Write (PUT) High level Normal read Normal read Wait release Normal write Outputs the contents of the MSB at the falling edge of the shift clock. The clock counter is not reset. Clock Data MSB PUT SIO1SFR, DBF Low level Not written normally. The contents of SIO1SFR are destroyed. 226 PD17068 15.3.8 Serial Interface 1 Operation Table 15-9 summarizes serial interface 1 operation. Table 15-9 Serial Interface 1 Operation Operation mode Serial interface 1 Slave operation (both SIO1CK1 and SIOICK0 are 0) Master operation (both SIO1CK1 and SIO1CK0 are not 0) Waiting (SIO1TS = 0) Outputs high level regardless of P2DIO0. When the state of the pin is read at this time, the contents of the output latch are read. Wait released (SIO1TS = 1) Outputs the internal clock regardless of P2DBIO0. When the state of the pin is read at this time, the contents of the output latch are read. Item State of each pin SCK1/P2D0 Waiting (SIO1TS = 0) Wait released (SIO1TS = 1) q When P2DBIO0 = 0, q When P2DBIO0 = 0, works as a generalis floating and waitpurpose input port, ing for external clock and is floating. input. q When P2DBIO0 = 1, q When P2DBIO0 = 1, works as a generalworks as a generalpurpose output port. purpose output port. Outputs the conOutputs the contents of the output latch. SO1/P2D1 tents of the output latch. SIO1HIZ = 0 q When P2DBIO1 = 0, works as a general-purpose input port and is floating. q When P2DBIO1 = 1, works as a general-purpose output port. Outputs the contents of the output latch. SIO1HIZ = 1 Outputs high level regardless of P2DBIO1. When the state of the pin is read at this time, the contents of the output latch are read. Outputs serial data regardless of P2DBIO1. When the state of the pin is read at this time, the contents of the output latch are read. Outputs high level regardless of P2DBIO1. When the state of the pin is read at this time, the contents of the output latch are read. Outputs serial data regardless of P2DBIO1. When the state of the pin is read at this time, the contents of the output latch are read. SI1, P2D2 q When P2DBIO2 = 0, is floating and waiting for external data input. q When P2DBIO2 = 1, works as a general-purpose output port. Outputs the contents of the output latch. Incremented at the rising edge of the SCK1 pin signal. Clock counter Presettable shift register 1 operation Output q When P2DBIO2 = 0, not output. q When P2DBIO2 = 1, shifts and outputs the data from the SO1 pin from the MSB at the falling edge of the SCK1 pin signal. Input Shifts and inputs the data from the LSB at the rising edge of the SCK1 pin signal regardless of P2DBIO2. However, when P2DBIO2 = 1, outputs the contents of the output latch from the SI1 pin. 227 PD17068 15.3.9 State When Serial Interface 1 Is Reset (1) At power-on reset All the pins are set to general-purpose input ports. The contents of presettable shift register 1 are undefined. (2) At clock-stop All the pins are set to general-purpose input ports. The contents of presettable shift register 1 retain their previous state. (3) At CE reset All the pins are set to general-purpose input ports. The contents of presettable shift register 1 retain their previous state. (4) At halt All the pins retain their set states. The internal clock stops output when a HALT instruction is executed. If an external clock is used, operation continues even if a HALT instruction is executed. 228 PD17068 16. IMAGE DISPLAY CONTROLLER (IDC) The IDC is used to display the channel No., volume, timer clock, etc. on a TV screen. 16.1 16.1.1 GENERAL Configuration Fig. 16-1 outlines the IDC. The display pattern is set in the CROM (Character ROM) area by program. The VRAM (Video RAM) stores the data for selecting the actual display pattern from the CROM. VRAM is allocated to BANK2 of the data memory. (See Fig. 4-2.) Fig. 16-1 IDC IDCEN flag IDCISEL flag IDCD14SL flag IDCCPCH flag IDCBKEN flag IDCBKR flag IDCBKG flag IDCBKB flag DBF 10 VRAM pointer Address read IRQIDCVP flag HSYNC VSYNC RED GREEN BLUE BLANK P0B2/I Control data IDC display control block VRAM Addressing CROM Character pattern data VRAMSEL flag IDC start position control block 8 DBF Remarks 1. IDCEN (bit 0 of IDC enable register: see Fig. 16-2) sets IDC display ON/OFF. 2. IDCISEL (bit 2 of IDC mode selection register: see Fig. 16-3) selects the POB2/I pin function. 3. IDCD14SL (bit 1 of IDC mode selection register: see Fig. 16-3) sets the number of vertical dots of the display character. 4. IDCCPCH (bit 0 of IDC mode selection register: see Fig. 16-3) sets whether or not there is a space between display characters. 5. IDCBKEN (bit 3 of IDC background selection register: see Fig. 16-4) sets whether or not a screen background is displayed. 6. IDCBKR, IDCBKG, and IDCBKB (bits 2, 1 and 0 of IDC background selection register: see Fig. 16-4) set the screen background color. 7. VRAMSEL (bit 3 of IDC mode selection register: see Fig. 16-3) sets whether or not there is a VRAM area. 229 PD17068 16.1.2 IDC Functions Table 16-1 summarizes the IDC functions. Table 16-1 IDC Functions Item Number of display characters Display position adjustment range Display format Function Maximum 192 characters/screen (full screen possible by program) Within horizontal 24 characters, vertical 15 rows (8 lines x 24 columns mode) 16 x 16 dot mode: 15 lines x 24 columns 14 x 16 dot mode: 17 lines x 24 columns Operation data -- Control data IDCD14SL flag Character set (font) Character size 255 kinds (user-programmable) Vertical: 14 sizes (1-14 times, line units) Horizontal: 24 sizes (1-24 times, character units) Character pattern data Control data Space between characters Character color Character background color Screen background color 0/2 bit (The size of one dot depends on the character size.) 16 kinds (character units) 8 kinds (character units) 8 kinds (set for 1 screen) IDCCPCH flag Character pattern data Control data IDCBKEN flag IDCBKR flag IDCBKG flag IDCBKB flag Control data Character pattern data Character pattern data Character rimming Rim (character units) Reverse video, rounding (character units) 230 PD17068 16.2 IDC DISPLAY CONTROL BLOCK The IDC display control block controls IDC display on/off, VRAM, space between display characters, display format, I pin use, and the screen background color. 16.2.1 IDC Display Control Block Control Registers The IDC display control block is controlled by IDC enable register, IDC mode selection register, and IDC background selection register. Figs. 16-2 to 16-4 show the organization and functions of each register. Fig. 16-2 Configuration of IDC Enable Register Flag symbol Register b3 b2 b1 b0 I D C E N Address Read/write IDC enable register 0 0 0 31H R/W Sets IDC display on/off. 0 1 Display off Display on Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Caution When setting the IDCEN flag to "1" (at the start of display), do it while the vertical synchronizing signal is high level (vertical flyback time, VSYNC, is low). 231 PD17068 Fig. 16-3 Configuration of IDC Mode Selection Register Flag symbol Register b3 V R A M S E L b2 I D C I S E L b1 I D C D 1 4 S L b0 I D C C P C H Address Read/write IDC mode selection register 33H R/W Sets whether or not there is a space between display characters. 0 1 No space Space Sets the number of vertical dots of the display character. 0 1 16 dots 14 dots Selects the function of the POB2/I pin. 0 1 General-purpose I/O port I pin Enables/disables the VRAM. 0 1 VRAM disable VRAM enable Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 232 PD17068 Fig. 16-4 Configuration of IDC Background Selection Register Flag symbol Register b3 I D C B K E N b2 I D C B K R b1 I D C B K G b0 I D C B K B Address Read/write IDC background selection register 30H R/W Sets the screen background color. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 No background (black) Blue Green Cyan Red Magenta Yellow White Sets whether or not screen background is displayed. 0 1 Do not display screen background color. Display screen background color. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 16.2.2 Display Format When the IDCD14SL flag of the IDC mode selection register is set (1), 14 vertical x 16 horizontal dots is selected. When it is reset (0), 16 vertical x 16 horizontal dots is selected. When you want to display 17 lines on one screen, select the 14 x 16 dots mode. 16.2.3 Space between Characters A 2-dot space can be set in front of a character by setting the IDCCPCH flag of the IDC mode selection register. The size of the space depends on the character size (horizontal). When a space is not set, kanji and other characters and graphics can be displayed by combining two or more characters. 233 PD17068 Fig. 16-5 Space between Characters q When IDCCPCH flag is "0" q When IDCCPCH flag is "1" 2-dot space 234 PD17068 16.2.4 Screen Background Color The background color of the entire display screen can be set by manipulating the IDC background selection register flags. The character color and screen background color can be set simultaneously. The display priority is: Character color < character background color < screen background color 16.3 IDC START POSITION CONTROL BLOCK The IDC start position control block can shift the display position of the entire screen by setting data in the IDC start position setting register (IDCORG: peripheral address 01H). 16.3.1 Configuration of IDC Start Position Setting Register Fig. 16-6 shows the configuration of the IDC start position setting register. Set data when the VSYNC signal is low level. Fig. 16-6 Configuration of IDC Start Position Setting Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GET 8 PUT Peripheral register Register IDC start position setting register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address IDCORG 01H DBF0 Valid data Vertical start position setting 0 Vertical start position (number of scanning lines from trailing edge of vertical synchronizing signal) = 16 + 1 x x (lines) x 15 (FH) Horizontal start position setting 0 Horizontal start position (when IDC LC oscillation is 10 MHz) = 3.2 s + 100 ns x x x 15 (FH) 235 PD17068 16.3.2 Horizontal Start Position Setting When the data set in the horizontal start position setting register is "0H" and OSCIN = 10 MHz, the horizontal start position is set to 3.2 s (2 characters) after the trailing edge of the horizontal synchronizing signal. Each time this data is increased by "1", the horizontal start position is shifted 100 ns (1 dot of minimum size character) to the right. That is, it can be expressed as follows: Horizontal start position = 3.2 s + 100 ns x (horizontal start position setting data) Referring to Fig. 16-7, assume that the position is A when the horizontal start position setting register set value is "0H." When the set value is made "1H", the horizontal start position moves 100 ns to the right and becomes position B. Fig. 16-7 Horizontal Direction Movement 3.2 s after trailing edge of horizontal synchronizing signal IDC image area A B Remarks : Image area when horizontal position set data is "0H" : Image area when horizontal position set data is "1H" 236 PD17068 16.3.3 Vertical Start Position Setting When the data set in the vertical start position setting register is "0H", the vertical start position is set to 16 scanning lines after the trailing edge of the vertical synchronizing signal. Each time this data is increased by "1", the vertical start position is moved down 1 line. This can be expressed as follows: Vertical start position = 16 + 1 x (vertical start position setting data) Referring to Fig. 16-8, assume that the vertical start position is A when the vertical start position setting register set value is "0H." When the set value is made "1H", the vertical start position is moved down 1 line to position B. Fig. 16-8 Vertical Direction Movement 16H after trailing edge of vertical synchronizing signal A IDC image area B Remarks : Image area when vertical position setting data is "0H" : Image area when vertical position setting data is "1H" 237 PD17068 The display character vertical start position is determined by the vertical start position register. The vertical start position (counted by the number of horizontal scanning lines) at this time is selected as shown in Fig. 16-9, according to the state of the VSYNC and HSYNC signals that are input at the VSYNC and HSYNC pins. In short, the first HSYNC signal after the rising edge of the VSYNC signal is counted as the first line. Fig. 16-9 How Vertical Start Position Is Counted VSYNC HSYNC HSYNC Remark #, $, or % indicates the number of each scanning line. 238 PD17068 16.4 CROM (CHARACTER ROM) The CROM stores the IDC display pattern data (character pattern data). Fig. 16-10 shows the configuration of the CROM. CROM is allocated to CROM area (3000H-4FDFH) in program memory (ROM). The CROM area cannot be used as normal program memory. CROM is addressed with VRAM character pattern selection data. CROM stores the data of 4080 steps (4080 x 24 bits: 255 characters), but since one address occupies 32 bits, its actual capacity is 8160 x 16 bits. (See Fig. 2-2.) Fig. 16-10 Configuration of CROM Real address CROM address Normal program memory 2FFFH 3000H 00H 301FH Bits 7 to 0 of character pattern selection data Addressing Character pattern data for one character 3000H Character data 3001H Rim data Rim data (Dummy) CROM area 4FC0H FEH 4FDFH 16 bits 301EH 301FH 239 PD17068 16.4.1 Character Pattern Data Configuration The character pattern data is used for displaying characters and graphic patterns. One character consists of 16 horizontal dots by 16 vertical dots. Since the data for 16 horizontal dots corresponds to one step of CROM, the character pattern data for one character consists of 16 steps (16 x 24 bits). Fig. 16-11 shows the configuration of the character patterns. The 8 low-order bits of the character pattern data are fixed at "1" (dummy). The character data that stores the actual display pattern consists of 8 bits. The bits corresponding to the dots that are lit are set to "1" and the bits corresponding to the dots that are not lit are set to "0". Two dots of the actual display pattern correspond to one bit of character pattern data. A character pattern data is formed by dot image by superimposing 16-bit rim data (in dot units) onto the character data. If a 17K Series assembler (AS17K) is used, data like that shown in Fig. 16-12 can be generated automatically by using a DCP pseudo instruction. A display pattern generation development tool (IDC font editor) is also available. Use this tool, if necessary. Fig. 16-11 Configuration of Character Data Pattern b31 Character data b24 b23 Rim data b8 b7 Dummy (Fixed to 1.) b0 Examples of character pattern data are shown in Fig. 16-12. In this data, "0" corresponds to s and "1" corresponds to s. The control data specifies the character size, position, and color. 240 PD17068 Fig. 16-12 Character Pattern Data Setting (Character: "N") q Character pattern Real address xxx0H xxx1H xxx2H xxx3H xxx4H xxx5H xxx6H xxx7H xxx8H xxx9H xxxAH xxxBH xxxCH xxxDH xxxEH xxxFH xxx0H xxx1H xxx2H xxx3H xxx4H xxx5H xxx6H xxx7H xxx8H xxx9H xxxAH xxxBH xxxCH xxxDH xxxEH xxxFH b31 b24 b23 b16 b15 b8 b7 b0 00000000 00100010 00100011 01110010 01110010 00110110 00110110 00111100 01111100 01111100 01011100 01011100 11011100 11001000 11001000 00000000 00000100 00000100 00001010 00001010 00010010 00010001 00100001 00010010 00100001 00010100 00010000 10100100 00010000 10100100 00010000 01101000 00100000 01001000 00100100 00001000 01001100 00010000 01001010 00010000 10010010 00010000 10001001 00100000 10010001 00100000 01100000 11000000 11111111 Dummy 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 Character data q Rim data Setting when a DCP pseudo instruction is used ; Display_N : DB 04H, 04H, 00H, 0FFH DB 0AH, 0AH, 22H, 0FFH DB 11H, 12H, 23H, 0FFH DB 12H, 21H, 72H, 0FFH DB 14H, 21H, 72H, 0FFH DB 0A4H, 10H, 36H, 0FFH DB 0A4H, 10H, 36H, 0FFH DB 68H, 10H, 3CH, 0FFH DB 48H, 20H, 7CH, 0FFH DB 08H, 24H, 7CH, 0FFH DB 10H, 4CH, 5CH, 0FFH DB 10H, 4AH, 5CH, 0FFH DB 10H, 92H, 0DCH, 0FFH DB 20H, 89H, 0C8H, 0FFH DB 20H, 91H, 0C8H, 0FFH DB 0C0H, 60H, 00H, 0FFH Conversion with a DCP pseudo instruction DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP DCP ' # # ' #O# #O# ' #OO# #OOO# ' #OOOO# #OO# ' #OOOO# #O# ' #OOOO# #OO# ' #OOOO# #OO# ' #OOOOO##O# ' #OOOOOO#OO# ' #OO#OOOOOO# ' #OO#OOOOOO# ' #OO# #OOOO# ' #OO# #OOOO# ' #OOO# #OO# ' #OO# #OO# ' ## ## ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 241 PD17068 16.4.2 Definition of Character Pattern Data with Assembler Character data can be easily defined with a 17K Series assembler by using a DCP pseudo instruction. The DCP pseudo instruction description is shown below. (1) Format Symbol field [Label:] Mnemonic field DCP Operand field `display pattern' Comment field [:comment] (2) Description The display pattern uses only the three characters "O", "#", and " " (blank). Sixteen characters are described on one line. If a character other than these three characters is described, or if less than 16 characters are described, an error is generated. Each of these three characters corresponds to one dot of the display pattern and has the following meaning: "O" : Dot to be displayed (lit) "#" : Rim " " : Blank (3) Assembly method Before a file describing characters with a DCP pseudo instruction is assembled, it must be converted to a source file. Perform this conversion as follows: # $ % Create a file defining the character using a DCP pseudo instruction. Make the extension DCP. Convert the file created at step DCP.EXE ( xxx.DCP # to a source file by executing program DCP.EXE as follows: : space, xxx.DCP: File name of created file) When the program ends, a xxx.ASM file is created. Assemble this file. 242 PD17068 16.5 16.5.1 VRAM (VIDEO RAM) General Fig. 16-13 shows the configuration of the VRAM. Fig. 16-14 shows VRAM bank specification. The VRAM stores the following three kinds of data: q q q Character pattern selection data Carriage return data (C/R) Control data 1 and 2 The VRAM is allocated at addresses 00H-3FH of BANK 2 of data memory, and is enabled only when the VRAMSEL flag is "1". When the VRAMSEL flag is set to "1", neither VRAM nor RAM exist at addresses 30H3FH of data memory and "0" is always read from this area. VRAM consists of 14 banks designated VRAMBANK0 to VRAMBANKD. (See Fig. 4-2.) The data at address 73H of BANK 2 of data memory specifies the VRAM BANK. One item of VRAM data consists of data at 3 addresses (12 bits). Each bank consists of 48 nibbles. Twohundred twenty-three data items can be set as VRAM data. Fig. 16-13 Configuration of VRAM Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F VRAMBANK0-D 0 1 Row address 2 3 4 5 6 7 BANK 2 Fixed to 0. System register Specifies the VRAM bank. Column address 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 4 bits Row address 1 4 bits VRAM data (at 3 addresses) 2 4 bits 243 PD17068 Fig. 16-14 VRAM Bank Specification VRAMSEL = 0 VRAMSEL = 1 VRAM (BANK0) RAM (BANK2) VRAMSEL = 1 VRAM (BANKB) Fixed to 0. Fixed to 0. RAM (BANK2) RAM (BANK2) 73H "0000" 73H "1011" 16.5.2 Configuration of VRAM Data Fig. 16-15 shows the configuration of the VRAM data. One item of VRAM data consists of 12 bits, and is divided into an ID field and a data field. Fig. 16-15 Configuration of VRAM Data 0xH Address b11 b10 Name ID b9 b8 b7 1xH b6 b5 b4 b3 2xH b2 b1 b0 Data field q ID field The ID field represents the state of the character pattern selection data. The ID field settings and character pattern selection data states are shown in Table 16-2. For details, see Section 16.5.5. Table 16-2 ID Field Settings and Character Pattern Selection Data States ID field setting 0 Note Character pattern selection data state When combined with control data 2 When combined with control data 1 0 or 1 Note Becomes carriage return data only when the ID field is 0 and the data field has the following value: q q q 10111111111 ... VRAM pointer reset C/R 11011111111 ... Line C/R 11111111111 ... Screen C/R 244 PD17068 16.5.3 Character Pattern Selection Data Fig. 16-16 shows the configuration of the character pattern selection data. A "character pattern" is data that specifies the shape and other attributes of the character displayed on a television set or other screen and is stored in the CROM (Character ROM). Bits 8 to 10 of the character pattern selection data specify the character color. Bits 0 to 7 are the CROM address. Table 16-3 shows the correspondence between the CROM address specified by the character pattern selection data and the real address. For the CROM, see Section 16.4. Fig. 16-16 Configuration of Character Pattern Selection Data b11 b10 ID Character color b8 b7 CROM address b0 b10 0 0 0 0 1 1 1 1 b9 0 0 1 1 0 0 1 1 b8 0 1 0 1 0 1 0 1 Set the character color. Black Blue Green Cyan Red Magenta Yellow White 245 PD17068 Table 16-3 CROM Address Specified by Character Pattern Selection Data and Real Address (1/2) CROM address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Real address CROM address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Real address CROM address 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH Real address CROM address 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Real address 3000H-301FH 3020H-303FH 3040H-305FH 3060H-307FH 3080H-309FH 30A0H-30BFH 30C0H-30DFH 30E0H-30FFH 3100H-311FH 3120H-313FH 3140H-315FH 3160H-317FH 3180H-319FH 31A0H-31BFH 31C0H-31DFH 31E0H-31FFH 3200H-321FH 3220H-323FH 3240H-325FH 3260H-327FH 3280H-329FH 32A0H-32BFH 32C0H-32DFH 32E0H-32FFH 3300H-331FH 3320H-333FH 3340H-335FH 3360H-337FH 3380H-339FH 33A0H-33BFH 33C0H-33DFH 33E0H-33FFH 3400H-341FH 3420H-343FH 3440H-345FH 3460H-347FH 3480H-349FH 34A0H-34BFH 34C0H-34DFH 34E0H-34FFH 3500H-351FH 3520H-353FH 3540H-355FH 3560H-357FH 3580H-359FH 35A0H-35BFH 35C0H-35DFH 35E0H-35FFH 3600H-361FH 3620H-363FH 3640H-365FH 3660H-367FH 3680H-369FH 36A0H-36BFH 36C0H-36DFH 36E0H-36FFH 3700H-371FH 3720H-373FH 3740H-375FH 3760H-377FH 3780H-379FH 37A0H-37BFH 37C0H-37DFH 37E0H-37FFH 3800H-381FH 3820H-383FH 3840H-385FH 3860H-387FH 3880H-389FH 38A0H-38BFH 38C0H-38DFH 38E0H-38FFH 3900H-391FH 3920H-393FH 3940H-395FH 3960H-397FH 3980H-399FH 39A0H-39BFH 39C0H-39DFH 39E0H-39FFH 3A00H-3A1FH 3A20H-3A3FH 3A40H-3A5FH 3A60H-3A7FH 3A80H-3A9FH 3AA0H-3ABFH 3AC0H-3ADFH 3AE0H-3AFFH 3B00H-3B1FH 3B20H-3B3FH 3B40H-3B5FH 3B60H-3B7FH 3B80H-3B9FH 3BA0H-3BBFH 3BC0H-3BDFH 3BE0H-3BFFH 3C00H-3C1FH 3C20H-3C3FH 3C40H-3C5FH 3C60H-3C7FH 3C80H-3C9FH 3CA0H-3CBFH 3CC0H-3CDFH 3CE0H-3CFFH 3D00H-3D1FH 3D20H-3D3FH 3D40H-3D5FH 3D60H-3D7FH 3D80H-3D9FH 3DA0H-3DBFH 3DC0H-3DDFH 3DE0H-3DFFH 3E00H-3E1FH 3E20H-3E3FH 3E40H-3E5FH 3E60H-3E7FH 3E80H-3E9FH 3EA0H-3EBFH 3EC0H-3EDFH 3EE0H-3EFFH 3F00H-3F1FH 3F20H-3F3FH 3F40H-3F5FH 3F60H-3F7FH 3F80H-3F9FH 3FA0H-3FBFH 3FC0H-3FDFH 3FE0H-3FFFH 246 PD17068 Table 16-3 CROM Address Specified by Character Pattern Selection Data and Real Address (2/2) CROM address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH Real address CROM address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH Real address CROM address C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH Real address CROM address E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH Real address 4000H-401FH 4020H-403FH 4040H-405FH 4060H-407FH 4080H-409FH 40A0H-40BFH 40C0H-40DFH 40E0H-40FFH 4100H-411FH 4120H-413FH 4140H-415FH 4160H-417FH 4180H-419FH 41A0H-41BFH 41C0H-41DFH 41E0H-41FFH 4200H-421FH 4220H-423FH 4240H-425FH 4260H-427FH 4280H-429FH 42A0H-42BFH 42C0H-42DFH 42E0H-42FFH 4300H-431FH 4320H-433FH 4340H-435FH 4360H-437FH 4380H-439FH 43A0H-43BFH 43C0H-43DFH 43E0H-43FFH 4400H-441FH 4420H-443FH 4440H-445FH 4460H-447FH 4480H-449FH 44A0H-44BFH 44C0H-44DFH 44E0H-44FFH 4500H-451FH 4520H-453FH 4540H-455FH 4560H-457FH 4580H-459FH 45A0H-45BFH 45C0H-45DFH 45E0H-45FFH 4600H-461FH 4620H-463FH 4640H-465FH 4660H-467FH 4680H-469FH 46A0H-46BFH 46C0H-46DFH 46E0H-46FFH 4700H-471FH 4720H-473FH 4740H-475FH 4760H-477FH 4780H-479FH 47A0H-47BFH 47C0H-47DFH 47E0H-47FFH 4800H-481FH 4820H-483FH 4840H-485FH 4860H-487FH 4880H-489FH 48A0H-48BFH 48C0H-48DFH 48E0H-48FFH 4900H-491FH 4920H-493FH 4940H-495FH 4960H-497FH 4980H-499FH 49A0H-49BFH 49C0H-49DFH 49E0H-49FFH 4A00H-4A1FH 4A20H-4A3FH 4A40H-4A5FH 4A60H-4A7FH 4A80H-4A9FH 4AA0H-4ABFH 4AC0H-4ADFH 4AE0H-4AFFH 4B00H-4B1FH 4B20H-4B3FH 4B40H-4B5FH 4B60H-4B7FH 4B80H-4B9FH 4BA0H-4BBFH 4BC0H-4BDFH 4BE0H-4BFFH 4C00H-4C1FH 4C20H-4C3FH 4C40H-4C5FH 4C60H-4C7FH 4C80H-4C9FH 4CA0H-4CBFH 4CC0H-4CDFH 4CE0H-4CFFH 4D00H-4D1FH 4D20H-4D3FH 4D40H-4D5FH 4D60H-4D7FH 4D80H-4D9FH 4DA0H-4DBFH 4DC0H-4DDFH 4DE0H-4DFFH 4E00H-4E1FH 4E20H-4E3FH 4E40H-4E5FH 4E60H-4E7FH 4E80H-4E9FH 4EA0H-4EBFH 4EC0H-4EDFH 4EE0H-4EFFH 4F00H-4F1FH 4F20H-4F3FH 4F40H-4F5FH 4F60H-4F7FH 4F80H-4F9FH 4FA0H-4FBFH 4FC0H-4FDFH 247 PD17068 16.5.4 Carriage Return Data (C/R) Fig. 16-17 shows the kinds of carriage return data. There are the following three kinds of carriage return data. Data other than these functions as character pattern selection data. q q q Line C/R VRAM pointer reset C/R Screen C/R When displaying data exceeding the VRAM capacity (extended display mode) on one page, set VRAM pointer reset C/R data at the end of the VRAM. For a description of the extended display mode, see Section 16.8. Fig. 16-17 Kinds of Carriage Return Data b11 Line C/R 0 b10 1 b9 1 b8 0 b7 1 b6 1 b5 1 b4 1 b3 1 b2 1 b1 1 b0 1 VRAM pointer reset C/R 0 1 0 1 1 1 1 1 1 1 1 1 Screen C/R 0 1 1 1 1 1 1 1 1 1 1 1 16.5.5 Control Data Fig. 16-18 shows the configuration of the control data. "Control data" is used for specifying the character size, display position, and color on the character pattern screen. There are the following two kinds of control data: q q Control data specified at each line (control data 1) Control data specified for each character (control data 2) Control data 1 is represented by 12 bits following VRAM address 0 (after screen C/R) and the line C/R. Control data 2 is represented by 12 bits following the character data when the ID field is set to "1". In short, it is used as a pair with the character pattern selection data. Control data 2 modifies the character up to control data 2 directly preceding it or up to the screen C/R. Specify control data 1 for each line whether or not it has changed. 248 PD17068 # Control data 1 b11 Vertical size b8 b7 Vertical position b4 b3 Horizontal position b0 $ Control data 2 b11 1 Character pattern selection data b10 b0 b11 0 b10 Horizontal size b6 b5 Rim b4 Character background color b1 b0 Color density Control data 2 (1) Functions of control data 1 # Character vertical size setting (bits 8-11) Table 16-4 lists the settings and corresponding character attributes. Fourteen sizes (1X-14X) can be set for each line. Table 16-4 Vertical Size Setting Control data 1 Size b11 0 0 0 0 b10 0 0 0 0 b9 0 0 1 1 b8 0 1 0 1 1X 2X 3X 4X Maximum number Vertical width of vertical display of 1 character characters (in interlace mode) 16H 32H 48H 64H 8 4 2 2 1 1 1 1 0 0 0 1 13X 14X 208H 224H 1 1 249 PD17068 $ Character vertical position setting (bits 4-7) Bits 4 to 7 of control data 1 set the vertical position from which display starts for each line. This setting is performed for each line. The line display position is represented by the number of dots from the last line. The set value itself becomes the line spacing. Table 16-5 lists the settings and corresponding vertical positions. Set the display start position of the entire screen at the IDC start position setting register (IDCORG). Remark One dot refers to that used when the vertical size is 1X. It does not change even when the vertical size is set to a value other than 1X. Table 16-5 Vertical Position Setting Control data 1 Vertical spacing b7 0 0 0 b6 0 0 0 b5 0 0 1 b4 0 1 0 Begin display 0 dots from preceding line Begin display 1 dot from preceding line Begin display 3 dots from preceding line 1 1 1 1 1 1 0 1 Begin display 14 dots from preceding line Begin display 15 dots from preceding line % Character horizontal position setting (bits 0-3) Bits 0 to 3 of control data 1 set the horizontal position from which the line is to be displayed. The horizontal position is represented by the number of dots shifted relative to the horizontal start position set by the IDC start position setting register (IDCORG). The set value itself becomes the number of dots the position is shifted. Table 16-6 lists the settings and corresponding horizontal positions. Remark One dot refers to that used when the horizontal size is 1X. 250 PD17068 Table 16-6 Horizontal Position Setting Control data 1 Horizontal spacing b3 0 0 0 b2 0 0 0 b1 0 0 1 b0 0 1 0 Begin display 0 dots from the position set by IDCORG Begin display 1 dot from the position set by IDCORG Begin display 2 dots from the position set by IDCORG 1 1 1 1 1 1 0 1 Begin display 14 dots from the position set by IDCORG Begin display 15 dots from the position set by IDCORG (2) Functions of control data 2 # Character horizontal size setting (bits 6-10) Table 16-7 lists the settings and corresponding character attributes. Twenty-four sizes (1X-24X) can be set for each character. Table 16-7 Horizontal Size Setting Control data 2 Size b10 0 0 0 0 0 0 0 b9 0 0 0 0 0 0 0 b8 0 0 0 1 1 1 1 b7 0 0 1 0 0 1 1 b6 0 1 0 0 1 0 1 1X 2X 3X 4X 5X 6X 7X Horizontal width of 1 character 1.6 s 3.2 s 4.8 s 6.4 s 8.0 s 9.6 s 11.2 s Maximum number of display characters in 1 line 24 12 8 6 4 4 3 1 1 0 1 1 0 1 0 1 0 23X 24X 36.8 s 38.4 s 1 1 Remark Since the horizontal size consists of 5 bits, up to 32X can be set as data. Although a value exceeding this may be set, because the number of columns per line is 24, the data will not displayed correctly. 251 PD17068 $ % Rim setting (bit 5) Bit 5 specifies rimming for the character pattern defined in CROM. When it is set to "0", rimming is not executed and when it is set to "1", rimming is executed. The rim color is black only. Character background color setting (bits 1-4) Table 16-8 lists the settings and corresponding background colors. The character background color is set by setting the control data of the first character of the character group to which the background color is applied. Bit 4 enables/disables character background color and bits 0 to 3 set the character background color. The character background color and screen background color can be set simultaneously. Table 16-8 Character Background Color Setting Control data 2 Character background color b4 0 1 1 1 1 1 1 1 1 b3 x 0 0 0 0 1 1 1 1 b2 x 0 0 1 1 0 0 1 1 b1 x 0 1 0 1 0 1 0 1 Blue Green Cyan Red Magenta Yellow White No background (black) Remark x : Don't care & Character color density (I output) setting (bit 0) Bit 0 sets the density of the character color. Up to 8 character colors can be specified. However, 16 colors can be specified by accompanying the specification with the color density. The density is set by setting "1" in bit 0 of control data 2 of the first character of the character group to which the density is to be set. Since the I output is also used for P0B2, when using it as the I pin, set the IDCISEL flag to 1. Remark The I output is output for all the dots regardless of the character dot size. When a space is set between characters, an I signal is output at the space also. 252 PD17068 16.5.6 VRAM Data Setting Example An example of VRAM data setting is shown in Fig. 16-19. Fig. 16-19 Example of VRAM Data Setting VRAMBANK 0 6 7 8 C O N T 2 C O N T 2 Character 0 0 1 2 3 C O N T 1 1 Character 2 Character 3 Character 4 Character 5 Character 9 Character A Character B Character C Character D Character E C O N T 2 F Character 0 C O N T 2 1 VRAMBANK 1 2 C O N T 1 Fixed to 0. Control data 1 is always set at the column address after column 0 of VRAMBANK 0 and line C/R. Fixed to 0. VRAMBANK D B Character C Character D Character E C O N T 2 F Character 0 C O N T 2 1 Line C/R 2 C O N T 1 3 Character 4 Character 5 Character 6 Screen C/R F Fixed to 0. Fixed to 0. The next control data 2 is valid for this character. Remarks CONT1 CONT2 Line C/R : Control data 1 : Control data 2 : C/R that indicates the end of 1 line Character : Character pattern selection data Screen C/R : C/R that indicates the end of 1 screen 16.5.7 VRAM Data Setting Cautions When setting data at the VRAM, begin from address 00H of VRAMBANK 0 in the state in which "2" is set in the BANK register and the VRAMSEL flag is set. # $ % VRAM is mapped to addresses 00H to 3FH of RAM bank 2. The area beginning from address 40H is normal RAM. The values at addresses 30H to 3FH are fixed to "0". Therefore, do not set the VRAM data after address 30H. When data is set at the VRAM by using index modification, the index-modified VRAM bank and VRAM row address may not be output for VRAM port only, but also for ports and system registers. The contents of the ports and system registers may be manipulated. (Data memory is not affected.) The hardware that is affected is shown in Table 16-9. Therefore, when the index modification addressing is used for the addresses shown in Table 16-9, write the data using a direct data memory operation instruction without using index modification (clear the IXE flag). Line C/R 253 PD17068 Table 16-9 Hardware Affected by Index Modification VRAM address after index modification VRAM bank 1, 5, 9, D VRAM address 2FH 30H to 32H 33H 34H to 3FH 3, 7, B 34H to 3FH Bank 2 2 2 -- -- Affected hardware Address 6FH 70H to 72H 73H 74H to 7FH 74H to 7FH Hardware name Port 2D Ports 2A-2C VRAM bank specification System registers System registers Caution Actually, there is no VRAM at VRAM addresses 30H to 3FH. Do not execute an instruction that operates these addresses. When an index register increment instruction is executed, in particular, the VRAM addresses may become 30H to 3FH. When setting data over multiple VRAM banks by using an increment instruction, proceed as follows: (1) Increment the VRAM address. When the address reaches 2FH, stop incrementing and clear the IXE flag. (2) Switch the VRAM bank and reset the index register. (3) Set the IXE flag again and start incrementing. & When the memory pointer is used to write data to the VRAM, ports and system registers may be operated in the same way as when index modification addressing is used. The hardware that is affected is the same as that shown in Table 16-9. However, since VRAM addresses 30H to 3FH are not VRAM area, do not set them in the memory pointer. When accessing address 2FH of VRAM banks 1, 5, 9, and D, do not use the memory pointer, but write data with a direct memory operation instruction. ( ) * + , - Always set control data 1 at the beginning of a line and a screen whether or not the data is to be changed. Set the character pattern selection data sequentially from the VRAM low address, in the order displayed from the top left of the screen. Always set the line carriage return data at the end of a line. Always set the VRAM pointer reset carriage return data at the end of the VRAM data when data exceeding the VRAM capacity (extended display mode) is displayed by program. Always set the screen carriage return data at the end of the data of a screen. When displaying data in the extended display mode, before reading the VRAM pointer reset carriage return data, rewrite the VRAM data at the first line that exceeds the VRAM capacity. 254 PD17068 16.6 16.6.1 VRAM POINTER Configuration of VRAM Pointer Fig. 16-20 shows the configuration of the VRAM pointer. The VRAM pointer generates an interrupt request at the specified VRAM address. Fig. 16-20 Configuration of VRAM Pointer DBF VRAM pointer buffer (IDCVP) VSYNC Line end signal Increment clock C/R detection Reset 10-bit counter Increment signal Match detection Interrupt request VRAM pointer register (IDCVPR) DBF 255 PD17068 16.6.2 VRAM Pointer Buffer (IDCVP) Fig. 16-21 shows the configuration of the VRAM pointer buffer. The VRAM buffer outputs the VRAM pointer value. Since the VRAM addresses at which the data has been already used for display can be identified by reading the VRAM pointer value, the VRAM data before the read address can be rewritten. Fig. 16-21 Configuration of VRAM Pointer Buffer Data buffer DBF3 DBF2 M S B DBF1 DBF0 L S B 0 0 0 0 0 0 Valid data GET 10 Peripheral register Name b9 M S B B3 B2 B1 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address L S B C2 C1 C0 VRAM pointer buffer Transfer data B0 R1 R0 C3 IDCVP 42H Remark Bn : VRAM bank Rn : VRAM row address Cn : VRAM column address 256 PD17068 16.6.3 VRAM Pointer Register (IDCVPR) Fig. 16-22 shows the configuration of the VRAM pointer register. The VRAM pointer register specifies the VRAM address at which an interrupt is to be generated. When the value set in the VRAM pointer register and the value of the VRAM pointer match, an interrupt request is issued. Therefore, VRAM data before the VRAM address set in the VRAM pointer register is rewritten in the interrupt routine. Fig. 16-22 Configuration of VRAM Pointer Register Data buffer DBF3 DBF2 Transfer data GET 16 PUT Peripheral register Register VRAM pointer register b15 b14 b13 b12 b11 b10 b9 0 0 0 0 0 0 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address IDCVPR 43H DBF1 DBF0 Valid data Sets the address at which an interrupt is to be generated, which is compared with the VRAM pointer 257 PD17068 16.7 16.7.1 IDC OUTPUT PINS (BLANK, RED, GREEN, BLUE, I PINS) Functions of IDC Output Pins The IDC output pins (BLANK, RED, GREEN, BLUE, I pins) are CMOS push-pull output pins and output an active high signal. The signal that blanks the broadcast image (blanking signal) is output from the BLANK pin and the character pattern signal (OR of R, G, B signals) is output from the RED, GREEN, BLUE, and I pins. 16.7.2 IDC Output Waveforms Fig. 16-23 shows the IDC output signal waveforms. When there is no rim, the blanking signal and character pattern signal output the same signal. When there is a rim, the blanking signal enveloping the character pattern signal is output from the BLANK pin. When the least significant bit of control data 1 is "1", the character pattern signal output from the I pin outputs high level for the display character only. Fig. 16-23 IDC Output Waveforms (1 Character) (a) When there is no rim Character pattern signal Blanking signal (b) When there is a rim Character pattern signal Blanking signal (c) I pin output 1 character RED, GREEN, BLUE pins I pin 258 PD17068 16.8 16.8.1 SAMPLE PROGRAM Displaying Data Exceeding VRAM Capacity (Extended Display Mode) Data exceeding the VRAM capacity can be displayed by applying an interrupt and rewriting the data that has already been displayed by program while VRAM data is being displayed on the screen. When displaying data in the extended display mode, set the VRAM pointer reset C/R at the end of the VRAM data. Normal screen display can be performed even when the character group to be displayed exceeds 8 lines as long as the VRAM data does not exceed the VRAM capacity. (1) Example of normal screen display exceeding 8 lines Column 0 1 Line 0 1 2 3 4 5 6 7 8 9 Line 10 L L S R O O F F L O O O E W W F D T P T I B R C F F S P P i E B A E T H n A A S B U U P K L S L R E E E S G H H H R E R O O R I I A E G G R E H H P N N N C 0 H 0 : 0 0 8 0 Column 16 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 259 PD17068 (2) Example in extended display mode When displaying a screen like the one shown below, use the extended display mode. Column 0 1 Line 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Line 16 0 1 2 3 4 5 6 7 8 9 A B C D E F G 1 2 3 4 5 6 7 8 9 A B C D E F G H Column 21 22 L M 0 1 2 3 4 5 6 7 8 9 A B C D E M 0 1 2 3 4 5 6 7 8 9 A B C D E F 2 2 3 4 5 6 7 8 9 A B C D E F G H I 3 3 4 5 6 7 8 9 A B C D E F G H I J 4 4 5 6 7 8 9 A B C D E F G H I J K 5 5 6 7 8 9 A B C D E F G H I J K L 6 6 7 8 9 A B C D E F G H I J K L M 7 7 8 9 A B C D E F G H I J K L M 0 8 8 9 A B C D E F G H I J K L M 0 1 9 9 A B C D E F G H I J K L M 0 1 2 10 A B C D E F G H I J K L M 0 1 2 3 11 12 B C D E F G H I J K L M 0 1 2 3 4 C D E F G H I J K L M 0 1 2 3 4 5 13 D E F G H I J K L M 0 1 2 3 4 5 6 14 15 16 E F G H I J K L M 0 1 2 3 4 5 6 7 F G H I J K L M 0 1 2 3 4 5 6 7 8 G H I J K L M 0 1 2 3 4 5 6 7 8 9 17 H I J K L M 0 1 2 3 4 5 6 7 8 9 A 18 I J K L M 0 1 2 3 4 5 6 7 8 9 A B 19 J K L M 0 1 2 3 4 5 6 7 8 9 A B C 20 K L M 0 1 2 3 4 5 6 7 8 9 A B C D The extended display mode flowchart is shown on the next page. 260 PD17068 (3) Flowchart The flowchart when one display data is displayed by rewriting the VRAM data once is shown below. Defines the DISP flag ("1" at second data display) as the flag that indicates if the IDC display uses the 1st VRAM data or 2nd VRAM data. Initializes the RAM, etc. Clears the DISP flag. Start Initialization Set 1st VRAM data Sets the VRAM pointer reset C/R at the end of the VRAM data. Set VRAM address at which interrupt request is to be issued, in IDCVPR Sets the 2nd data write timing. Must be set at least before the VRAM pointer reset C/R is read. Interrupt enable Starts IDC display. Checks if the VSYNC signal is low level and sets the IDCEN flag. IDCEN1 End Interrupt routine DISP = 1 ? YES NO Write 2nd VRAM data from VRAM top address Sets the screen C/R at the end of the VRAM data. Rewrite VRAM rewritten by 2nd VRAM data at 1st VRAM data Set VRAM address at which interrupt request is to be issued, in IDCVPR Sets the VRAM pointer reset C/R at the end of the VRAM data. Set VRAM address at which interrupt request is to be issued, in IDCVPR The interrupt timing must be before the end of display of the 2nd data. The interrupt timing must be before the end of display of the 2nd data. SET1 DISP Sets the DISP flag. CLR1 DISP Clears the DISP flag. Interrupt enable Interrupt enable RETI RETI 261 PD17068 17. HORIZONTAL SYNCHRONIZING SIGNAL COUNTER 17.1 GENERAL Fig. 17-1 outlines the horizontal synchronizing signal counter. The horizontal synchronizing signal counter counts the horizontal synchronizing signal (HSYNC signal) separated from the image signal sent from the broadcast station. It is counted up at the rising edge of the synchronizing signal. The frequency of the horizontal synchronizing signal can be found, and used to detect which broadcast station is using the frequency currently being received, by dividing the count value by the gate open time (set by HSYNC counter gate control register). Fig. 17-1 Horizontal Synchronizing Signal Counter P0B3/HSCNT Gate input amplifier ON/OFF HSYNC counter (6 bits) Gate clock generator 1.69 ms HSYNC counter data register (HSC) DBF HSCGT1 flag HSCGT0 flag HSCGOSTT flag Remarks 1. HSCGOSTT (bit 3 of HSYNC counter gate register: see Fig. 17-4): Detects opening and closing of the HSYNC counter gate. 2. HSCGT1 and HSCGT0 (bits 1 and 0 of the HSYNC counter gate control register: see Fig. 17-3) : Control opening and closing and the open time of the HSYNC counter gate. 17.2 GATE INPUT AMPLIFIER Fig. 17-2 shows the configuration of the gate input amplifier. The gate input amplifier is the self-bias type. To prevent erroneous operation by noise, use it without a coupling capacitor. Input the signal at a full amplitude of low level 0.2VDD or less and high level 0.8VDD or more. Fig. 17-2 Gate Input Amplifier P0B3/HSCNT To gate 262 PD17068 17.3 GATE CONTROL The HSYNC counter gate is controlled by the HSCGTx flag of the HSYNC counter gate control register and the HSCGOSTT flag of the HSYNC counter gate judge register. Figs. 17-3 and 17-4 show the organization and functions of the HSYNC counter gate control register and HSYNC counter gate judge register. The horizontal synchronizing signal counter input pin (HSCNT pin) is also used for P0B3. When using P0B3 as the HSCNT pin, set it to the input mode. If P0B3 is used as the HSCNT pin, when it is read, "0" is always read. When using P0B3 as a port, set the HSYNC counter gate control register to all "0". Fig. 17-3 Configuration of HSYNC Counter Gate Control Register Flag symbol Register b3 b2 b1 H S C G T 1 b0 H S C G T 0 Address Read/write HSYNC counter gate control register 0 0 11H R/W Controls the HSYNC counter gate. 0 0 1 1 0 1 0 1 Gate closed mode Gate open mode 1.69 ms gate open mode Not to be set. Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 0 0 263 PD17068 Fig. 17-4 Configuration of HSYNC Counter Gate Judge Register Flag symbol Register b3 H S C G O S T T b2 b1 b0 Address Read/write HSYNC counter gate judge register 0 0 0 12H R Fixed to 0. Detects opening and closing of the HSYNC counter gate. 0 1 Gate closed Gate open Upon reset Power-on Clock stop CE 0 0 0 0 17.3.1 HSYNC Counter Gate Mode Selection Flag (HSCGTx) The HSCGTx flag controls the HSYNC counter input gate clock. The following three modes can be selected: (a) Gate closed mode The gate clock generator does not operate and the gate remains closed. Therefore, the HSYNC counter does not operate. Self-biasing of the input pin is also disabled. When using HSCNT/P0B3 as a port, always select this mode. (b) Gate open mode After the gate is opened and the HSYNC counter is reset, counting of the HSYNC signal begins. The input pin is biased. (c) 1.69 ms gate open mode Counting of the HSYNC signal begins after a maximum delay of 8 ms after the gate is opened and the HSYNC counter is reset. The gate clock generator operates and the gate time becomes 1.69 ms. The input pin is biased. 17.3.2 open. In the 1.69 ms gate open mode, "1" is read from HSCGOSTT from the time the data was set even if a gate clock does not arrive. HSYNC Counter Gate Open Status Flag (HSCGOSTT) The HSCGOSTT flag detects the status of the HSYNC counter gate. It is normally set (1) while the gate is 264 PD17068 17.4 HSYNC COUNTER DATA REGISTER (HSC) Fig. 17-5 shows the configuration of the HSYNC counter data register. Fig. 17-5 Configuration of HSYNC Counter Data Register Data buffer DBF3 Hold DBF2 Hold DBF1 Transfer data GET 8 Peripheral register Register HSYNC counter data register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral register HSC 04H DBF0 Valid data HSYNC counter count value read 0 x Number of horizontal synchronizing signals 3FH (63) 17.5 SAMPLE PROGRAM A sample program for the horizontal synchronizing signal counter is shown below. Example 1.69 ms gate open mode INITFLG LOOP : SLF1 BR GET 17.6 STATE AT RESET HSCGOSTT LOOP DBF, HSC ; Detects the HSCGOSTT flag. ; And if the HSCGOSTT flag is "0", reads the count ; value at the data buffer. ; HSCGT1, NOT HSCGT0 ; Sets the HSYNC counter to the 1.69 ms gate ; open mode. At power-on reset, clock-stop, and CE reset, the gate is set to the gate closed mode and the HSYNC counter is reset. 265 PD17068 18. PLL FREQUENCY SYNTHESIZER The PLL (Phase Locked Loop) frequency synthesizer is used to lock VHF (Very High Frequency) band frequencies to a fixed frequency using a phase error comparison system. 18.1 GENERAL Fig. 18-1 outlines the PLL frequency synthesizer. A PLL frequency synthesizer can be built by connecting a low pass filter (LPF), voltage controlled oscillator (VCO), and prescaler externally. The PLL frequency synthesizer divides the signal input from the VCO using a programmable divider and outputs the phase error with the reference frequency to the EO pin. The PLL frequency synthesizer operates only when the CE pin is high level. When the CE pin is low level, the PLL frequency synthesizer is disabled. For a description of the PLL disabled state, see Section 18.5. Fig. 18-1 PLL Frequency Synthesizer PSC DBF VCO 1/8 1/16, 1/17 Programmable divider (PD) Phase comparator (o-DET) EO Charge pump Prescaler (PB595) Note 8 MHz Reference frequency generator Unlock detection block Low pass filter (LPF) Note Note Voltage controlled oscillator (VCO) PLLRFCK3 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag PLULSEN1 flag PLULSEN0 flag PLLUL flag Remarks 1. PLLRFCK3 to PLLRFCK0 (bits 0-3 of PLL reference clock selection register: see Fig. 18-5): Set the PLL frequency synthesizer reference frequency fr. 2. PLULSEN1 and PLULSEN0 (bits 1 and 0 of PLL unlock flip-flop sensibility selection register: see Fig. 18-9): Set the unlock flip-flop set delay time. 3. PLLUL (bit 0 of PLL unlock flip-flop judge register: see Fig. 18-8): Detects the state of the unlock flip-flop. Note External circuit. 266 PD17068 18.2 18.2.1 PROGRAMMABLE DIVIDER Configuration Fig. 18-2 shows the configuration of the programmable divider. The programmable divider divides the signal input from the VCO pin at the division ratio set by program. The division method is the pulse swallow method. The division value is set by the PLL data register through a data buffer. Fig. 18-2 Programmable Divider DBF 16 PLL data register PLL disable signal 12 bits 4 bits 4 12 VCO Swallow counter (4 bits) PSC Programmable counter (12 bits) fN To o-DET 267 PD17068 18.2.2 Programmable Divider and PLL Data Register The division value is set in the swallow counter and programmable counter by the PLL data register through a data buffer. The swallow counter and programmable counter are 4-bit and 12-bit binary down counters, respectively. Data is written to the PLL data register with the "PUT PLLR, DBF" instruction, and read from the PLL data register with the "GET DBF, PLLR" instruction. For a description of the division value (N value) setting method, see Section 18.6. (1) PLL data register and data buffer Fig. 18-3 shows the relationship between the PLL data register and the data buffer. All 16 bits of the PLL data register are valid. The 12 high-order bits are set in the programmable counter and the 4 low-order bits are set in the swallow counter. Fig. 18-3 PLL Data Register and Data Buffer Data buffer DBF3 DBF2 Transfer data GET 16 PUT Peripheral register Register PLL data register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address PLLR 41H DBF1 DBF0 Valid data Sets the division ratio used for the PLL frequency synthesizer. 0 Not to be set. 255 (00FFH) 256 (0100H) x Division ratio N: N=x 216 - 1 (FFFFH) 268 PD17068 (2) Relationship between programmable divider division value N and divided output frequency The relationship between the value "N" set in the PLL data register and the frequency "fN" of the signal divided and output by the programmable divider, is shown below. For details, see Section 18.6. fIN N fN = (fIN : Input frequency) 18.3 REFERENCE FREQUENCY GENERATOR Fig. 18-4 shows the configuration of the reference frequency generator. The reference frequency generator generates the PLL frequency synthesizer reference frequency "fr" by dividing the 8-MHz signal of a crystal oscillator. The reference frequency can be selected from among 5 kHz, 6.25 kHz, 10 kHz, 12.5 kHz, and 25 kHz. The reference frequency is selected with the PLLRFCKx flags of the PLL reference clock selection register. Fig. 18-5 shows the organization and functions of the PLL reference clock selection register. Fig. 18-4 Reference Frequency Generator PLLRFCK3 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag MUX 5 kHz 6.25 kHz 8 MHz Frequency divider 10 kHz 12.5 kHz 25 kHz OFF PLL disable signal To o-DET 269 PD17068 Fig. 18-5 Configuration of PLL Reference Clock Selection Register Flag symbol Register b3 P L L R F C K 3 b2 P L L R F C K 2 b1 P L L R F C K 1 b0 P L L R F C K 0 Address Read/write PLL reference clock selection register 13H R/W Sets the PLL frequency synthesizer reference frequency fr. 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 5 kHz 10 kHz 6.25 kHz 12.5 kHz 25 kHz PLL disabled Not to be set. Others Upon reset Power-on Clock stop CE 1 1 1 1 1 1 1 1 Hold Remark If PLL disabled is selected, the VCO pin is pulled down internally. The EO pin is floated. 270 PD17068 18.4 18.4.1 PHASE COMPARATOR (-DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK Configuration of Phase Comparator, Charge Pump and Unlock Detection Block Fig. 18-6 shows the configuration of the phase comparator, charge pump and unlock detection block. The phase comparator (-DET) compares the phase of the divided frequency (fN) signal output from the programmable divider and that of the reference frequency (fr) signal output from the reference frequency generator and outputs an up request signal (UP) or down request signal (DW). The charge pump outputs the output of the phase comparator from the error out pin (EO pin). The unlock detection block consists of a delay control circuit and an unlock flip-flop, and detects the PLL frequency synthesizer unlocked state. Sections 18.4.2 to 18.4.4 describe the operation of the phase comparator, charge pump, and unlock detection block. Fig. 18-6 Phase Comparator, Charge Pump and Unlock Detection Block PLULSEN1 flag PLULSEN0 flag PLLUL flag Reference frequency generator fr UP Delay control circuit Unlock flip-flop Phase comparator (o-DET) Unlock detection block Programmable divider fN DW Charge pump EO PLL disable signal 18.4.2 Phase Comparator Functions As shown in Fig. 18-6, the phase comparator compares the phase of the programmable divider divided (fN) output and that of the reference frequency (fr) signal and outputs an up request signal or down request signal. That is, if divided frequency "fN" is lower than reference frequency "fr", an up request signal is output, and if divided frequency "fN" is higher than reference signal "fr", a down request signal is output. Fig. 18-7 shows the relationship among the reference frequency fr, division frequency fN, up request signal, and down request signal. In the PLL disabled state, neither an up request signal nor a down request signal is output. The up request and down request signals are input to the charge pump and unlock detection block. 271 PD17068 Fig. 18-7 fr, fN, UP, and DW Signal Relationship (a) When fN phase lags fr phase fr fN UP DW (b) When fN phase leads fr phase fr fN UP DW (c) When fN and fr are same phase fr fN UP DW (d) When fN frequency lower than fr frequency fr fN UP DW 18.4.3 Charge Pump As shown in Fig. 18-6, the charge pump outputs the up request signal or down request signal sent from the phase comparator, from the error out pin (EO pin). Error output pin output, division frequency fN, and reference frequency fr have the following relation: When reference frequency fr > division frequency fN: Low level output When reference frequency fr < division frequency fN: High level output When reference frequency fr = division frequency fN: Floating 272 PD17068 18.4.4 Configuration and Functions of Unlock Detection Block As shown in Fig. 18-6, the unlock detection block detects the PLL frequency synthesizer unlocked state from the phase comparator up request and down request signals. That is, since the up request signal or down request signal outputs low level while the PLL frequency synthesizer is in the unlocked state, the unlocked state can be detected by monitoring this low level signal. When the PLL frequency synthesizer is in the unlocked state, the unlock flip-flop is set (1). The state of the unlock flip-flop is detected by the PLLUL flag of PLL unlock flip-flop judge register. The unlock flip-flop is set at the period of the reference frequency fr selected at the time. The contents of the PLL unlock flip-flop judge register are read (PEEK instruction) and reset (Read & Reset). The unlock flip-flop must be detected at a period longer than reference frequency fr period 1/fr. The delay control circuit controls the state that sets the unlock flip-flop by applying a delay to the phase comparator up request signal and down request signal. In other words, if the delay is long, the unlock flipflop is not set even if the phase deviation between the division frequency (fN) and reference frequency (fr) signals is large. The delay control circuit delay time is set with the PLL unlock flip-flop sensibility selection register. 18.4.5 Organization and Functions of PLL Unlock Flip-Flop Judge Register Fig. 18-8 shows the organization and functions of the PLL unlock flip-flop judge register. This register is a read only register, and is reset when the data is read and set to the window register using the "PEEK" instruction. Since the unlock flip-flop is set at the period of reference frequency fr, the PLL unlock flip-flop judge register must be read at the window register at a slower period than reference frequency period 1/fr. Fig. 18-8 Configuration of PLL Unlock Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 P L L U L Address Read/write PLL unlock flip-flop judge register 0 0 0 22H R & Reset Detects the state of the unlock flip-flop. 0 1 Unlock flip-flop = 0 : PLL locked Unlock flip-flop = 1 : PLL unlocked Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 * Hold Hold * Undefined 273 PD17068 18.4.6 Organization and Functions of PLL Unlock Flip-Flop Sensibility Selection Register Fig. 18-9 shows the organization and functions of the PLL unlock flip-flop sensibility selection register. When the unlock flip-flop disable state is set by the PLL unlock flip-flop sensibility selection register, the state of the unlock flip-flop is undefined. Fig. 18-9 Configuration of PLL Unlock Flip-Flop Sensibility Selection Register Flag symbol Register b3 b2 b1 P L U L S E N 1 b0 P L U L S E N 0 Address Read/write PLL unlock flip-flop sensibility selection register 0 0 32H R/W Sets the delay time between the reference (fr) and division frequency (fN) signals, which is necessary to set the unlock flip-flop. 0 0 1 1 0 1 0 1 1.25-1.5 s or more 3.5-37.5 s or more 0.25-0.5 s or more Unlock flip-flop disabled Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 0 0 Hold Hold 18.5 PLL DISABLED STATE The PLL frequency synthesizer is disabled while the CE pin is low level. The PLL frequency synthesizer is also disabled when PLL disabled is selected by the PLL reference clock selection register. Table 18-1 shows the state of each block at PLL disabled. Since the PLL reference clock selection register is not initialized (previous state is held) at CE reset, it is reset to its previous state when the CE pin rises to high level after dropping to low level and PLL disabled is set. Therefore, when PLL disabled must be set at CE reset, the PLL reference clock selection register must be initialized by program. At power-on reset, PLL disabled is set. 274 PD17068 Table 18-1 State of Each Block at PLL Disabled Block Reference frequency generator State Output stopped Output not stopped. Condition When PLLRFCKx = 1111B. CE pin = Low level When PLLRFCKx = 1111B (PLL disabled) or CE pin = Low level. Programmable counter Phase comparator Charge pump VCO pin PSC pin Frequency division stopped Output stopped Error output pin floated Pulled down internally Low level output 18.6 PLL FREQUENCY SYNTHESIZER USE To control the PLL frequency synthesizer, the following data is necessary: (1) Reference frequency: fr (2) Division value: N The PLL data setting method is shown below. (1) Reference frequency fr setting The reference frequency is set by the PLL reference clock selection register. (2) Division value N computation method Division value N is computed as follows: N= fVCO P x fr fVCO fr P (3) PLL data setting example The method of setting the data to receive a VHF band broadcast station is shown below. A PB595 is used as the prescaler. Computation is carried out with the fixed division ratio P of 8. Receiving frequency Reference frequency : 55.25 MHz : 5 kHz : VCO pin input frequency : Reference frequency : Prescaler division ratio Intermediate frequency : 45.75 MHz 275 PD17068 Division value N is: N= fVCO P x fr = 55250 + 45750 8x5 = 2525 (decimal) = 09DDH (hexadecimal) Data is written to the PLL data register and PLL reference clock selection register as follows: PLLR 0000 0 1001 9 1101 D 1101 D PLLRF 0010 5 kHz 18.7 SAMPLE PROGRAM A sample program for controlling the PLL frequency synthesizer is shown below. Example MOV POKE MOV POKE BANK0 MOV MOV MOV MOV PUT UL : DBF3, DBF2, DBF1, DBF0, PLLR, #xxxxB #xxxxB #xxxxB #xxxxB DBF ; Sets the division value in DBF (bit 0 of DBF0 is the LSB). ; ; ; ; Sets the division value into the swallow counter and programmable counter. ; n steps or more (fr period or more) Note 1 WR, PLLLOCK, WR, PLLRF, #00xxB WR #10xxB WR ; Sets the unlock flip-flop set signal delay time. ; ; Sets the reference frequency. SKF1 BR MOV POKE PLLUL UL WR, PLLLOCK, #0010B WR ; Sets the unlock flip-flop set signal delay time. Note 2 Notes 1. Read the unlock flip-flop at an interval greater than the reference frequency period. If the interval is shorter than this, the unlock flip-flop may not be read correctly, depending on the timing. 2. The first delay time is made maximum and PLL is locked loosely. Next, the delay time is made minimum and the PLL is locked fully. When this is done, viewed overall, the time until the PLL is locked can be shortened and the PLL locking precision can be raised. 276 ....................... PD17068 18.8 18.8.1 STATE AT RESET At Power-On Reset Since the PLL reference clock selection register is initialized to 1111B, the PLL disabled state is set. 18.8.2 At Clock-Stop The PLL disabled state is set at the time the CE pin drops to low level. 18.8.3 At CE Reset (1) CE reset caused by clock stop Since clock-stop initializes the PLL reference clock selection register to 1111B, the PLL disabled state is set. (2) CE reset when clock not stopped Since the PLL reference clock selection register retains its previous state, the previous state is set when the CE pin rises to high level. 18.8.4 During the Halt State If the CE pin is high level, the set state is held. 277 PD17068 19. STANDBY The standby function is used to reduce the supply current during back-up. 19.1 STANDBY FUNCTIONS Fig. 19-1 outlines the standby block. The standby block reduces the device current drain by stopping some, or all, operations of the device. The standby block has the following three functions. These functions can be used to suit the application. # $ % Halt function Clock-stop function Device operation control by CE pin The halt function reduces the device current drain by stopping CPU operation with a "HALT h" instruction. The clock-stop function reduces the device current drain by stopping the oscillation circuit with a "STOP s" instruction. Since the CE pin is used to control operation of the image display controller (IDC) and PLL frequency synthesizer and to reset the device, its operation control function is said to be a standby function. 278 PD17068 Fig. 19-1 Standby Block Halt block Interrupt control block Halt control circuit (HALT h) BTM0CY P0D2/ADC3 P0D1/ADC2/XTIN P0D0/ADC1/XTOUT Input latch P0D3/ADC4 CPU Program counter Instruction decoder Clock stop block RLSEN flag P1B2EDET flag P1B2/RLSSTP CE CE flag CEEDET flag ALU System register Clock-stop control circuit (STOP s) XOUT XIN Internal clock Control register Remarks 1. RLSEN (bit 0 of clock-stop release enable register: see Fig. 20-5): Releases clock-stop. 2. P1B2EDET (bit 0 of P1B2 pin edge detection register: see Fig. 19-6): Detects the rising edge input of the P1B2 pin. 3. CE (bit 0 of CE pin level judge register: see Fig. 19-8): Detects the status of the CE pin. 4. CEEDET (bit 0 of CE pin edge detection register: see Fig. 19-9): Detects the rising edge input of the CE pin. 279 PD17068 19.2 19.2.1 HALT FUNCTION General The halt function stops the CPU clock by executing a "HALT h" instruction. When a "HALT h" instruction is executed, the program halts and remains stopped until the halt state is released. In the halt state, the device current drain is reduced by the amount of the CPU operating current. The halt state is released by key input, basic timer 0 and interrupt. The release conditions are specified with the "h" operand of the HALT h instruction. The "HALT h" instruction is valid regardless of the CE pin input level. 19.2.2 Halt State In the halt state, all operations of the CPU are stopped. That is, the "HALT h" instruction stops program execution. However, the peripheral hardware remains in the state set before the "HALT h" is executed. For an operation description of each hardware device, see Section 19.4. 19.2.3 Halt Release Conditions Fig. 19-2 shows the halt release conditions. The halt release conditions are set with the 4-bit data specified by the "h" operand of the "HALT h" instruction. The halt state is released when the condition set to 1 at the "h" operand is satisfied. When the halt state is released, the program is executed from the instruction after the "HALT h" instruction. When multiple release conditions are set, the halt state is released if even one of the set conditions is satisfied. When reset (power-on reset or CE reset) is applied to the device, the halt state is released and the reset operations are performed. When 0000B is set at halt release condition "h", no halt condition is set. If reset (power-on reset or CE reset) is applied to the device at this time, the halt state is released. Fig. 19-2 Halt Release Conditions HALT h (4 bits) Operand b3 b2 b1 b0 0 : Do not release halt state even if condition satisfied. 1 : Release halt state when condition satisfied. Sets the halt state release conditions. Release when a high-level signal is input to port 0D. Release when the carry flip-flop for the basic timer 0 is set (1). Undefined (Fix it to "0".) Release when an interrupt is accepted. 280 PD17068 19.2.4 Halt Release by Key Input Halt release by key input is set by "HALT 0001B" instruction. When the halt release by key input is set, the halt state is released when high level is input at any one of the 0D port lines (P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN and P0D0/ADC1/XTOUT pins) Each 0D port pin has a built-in pull-down resistor. (1) When general-purpose output port is made key source P0D3/ADC4 Latch P0D2/ADC3 P0D1/ADC2/XTIN Switch A P0D0/ADC1/XTOUT General-purpose output port Execute a "HALT 0001B" instruction after the key source signal general-purpose output port is made high level. Note that if an alternate switch like switch A in the figure above is used, while switch A is closed, high level is applied to the P0D0/ADC1/XTOUT pin and the halt state is immediately released. (2) When P0D0/ADC1/XTOUT, P0D1/ADC2/XTIN, P0D2/ADC3, or P0D3/ADC4 pin used as A/D converter input A/D input P0D3/ADC4 A/D input Latch P0D2/ADC3 P0D1/ADC2/XTIN P0D0/ADC1/XTOUT General-purpose output port Avoid using the following method as much as possible. When the P0D0/ADC1/XTOUT, P0D1/ADC2/XTIN, P0D2/ADC3, or P0D3/ADC4 pin is selected as an A/D converter input, the selected pin (only one pin can be selected at one time) is disconnected from the input latch and connected to the internal A/D converter. If high level is unexpectedly input to the pin when it is selected as the A/D converter input, the latch circuit is held at high level. If a "HALT 0001B" instruction is executed in this state, the halt state is immediately released even when an instruction to make the input latch high level is executed because the latch has already been high level. 281 PD17068 (3) When used by connecting watchdog timer oscillator to P0D0/ADC1/XTOUT or P0D1/ADC2/XTIN pin P0D3/ADC4 P0D2/ADC3 P0D1/ADC2/XTIN Watchdog timer Latch P0D0/ADC1/XTOUT General-purpose output port Avoid the using the following method as much as possible. When the P0D0/ADC1/XTOUT or P0D1/ADC2/XTIN pin is selected as the watchdog timer oscillator connection pin, it is disconnected from the input latch and connected to the internal watchdog timer. If high level is unexpectedly input to the pin when it is selected as the watchdog timer oscillator connection pin, the latch circuit is held at high level. When a "HALT 0001B" instruction is executed in this state, the halt state is immediately released even if an instruction to make the input latch high level is executed because the latch has already been high level. (4) When halt released by other microcomputer, etc. Output port P0D3/ADC4 Latch P0D2/ADC3 Microcomputer, etc. P0D1/ADC2/XTIN P0D0/ADC1/XTOUT General-purpose output port The P0D0/ADC1/XTOUT, P0D1/ADC2/XTIN, P0D2/ADC3, and P0D3/ADC4 pins can be used as general-purpose input pins with pull-down resistors. Halt can be released by another microcomputer, etc. as shown in the figure above. 282 PD17068 19.2.5 Halt Release by Basic Timer 0 Halt release by basic timer 0 is set by the "HALT 0010B" instruction. When halt release by basic timer 0 is set, the halt state is released simultaneously with setting (1) of the carry flip-flop of basic timer 0. The carry flip-flop of basic timer 0 corresponds to the BTM0CY flag, and is set at a fixed cycle (1 ms, 5 ms or 100 ms). The halt state can be released at a fixed cycle. Example Program that releases the halt state every 100 ms and executes process A every second. M1 HLTTMR MEM DAT CLR2 0.10H 0010B BTMCK1, BTMCK0 ; 1 second counter ; Symbol definition ; Built-in macro ; Sets the cycle of the carry flip-flop of basic timer ; 0 to 100 ms. LOOP : HALT HLTTMR ; Sets the condition of release caused by the carry ; flip-flop of basic timer 0 and sets to the halt ; state. SKT1 BR ADD SKT1 BR Process A BR 19.2.6 LOOP BTM0CY LOOP M1, #0100B CY LOOP ; Built-in macro ; If BTM0CY flag is not set, branches to LOOP. ; Adds 0100B to contents of M1. ; Built-in macro ; If a carry is generated, executes process A. Halt Release by Interrupt Halt release by interrupt is set by the "HALT 1000B" instruction. When halt release by interrupt is set, the halt state is released simultaneously with acceptance of an interrupt. As described in Chapter 11, there are 10 interrupt sources. Therefore, which interrupt source releases the halt state must be specified by the program beforehand. To accept an interrupt, enable all interrupts (EI instruction) and enable each interrupt (interrupt enable flag set) must be satisfied, in addition to issuing an interrupt request from each interrupt source. Even if an interrupt request is issued, if that interrupt is not enabled, the interrupt is not accepted and the halt state is not released. If the halt state is released by acceptance of an interrupt, the program flow branches to the vector address of the interrupt. If an RETI instruction is executed after interrupt handling, the program flow returns to the instruction after the HALT instruction. 283 PD17068 Example HLTINT INTBTM2 INT0PIN START : BR ORG ORG INTBTM2 BR INT0PIN Process A BR INTTIMER : Process B EI_RETI : EI RETI MAIN : SET2 INITFLG IPBTM2, IP0 ; Built-in macro ; Built-in macro ; Sets basic timer 2 interrupt time interval to 1 ms. LOOP : Process C EI ; ; Main routine processing ; Enable all interrupts. HLTINT LOOP ; Sets halt release by interrupt. NOT BTM2EXCK, NOT BTM2ZX, BTM2CK1, NOT BTM2CK0 ; Basic timer 2 interrupt handling EI_RETI INTTIMER ; INT0 pin interrupt vector address (000AH) ; INT0 pin interrupt handling MAIN ; Basic timer 2 interrupt vector address (0006H) DAT DAT DAT 1000B 0006H 000AH ; Halt condition symbol definition ; Interrupt vector address symbol definition ; Interrupt vector address symbol definition ; Program address 0000H # HALT BR In the example above, when a basic timer 2 interrupt is accepted, the halt state is released and process B is executed. When an INT0 pin interrupt is accepted, process A is executed. Each time the halt state is released, process C is executed. When an INT0 pin interrupt request and a basic timer 2 interrupt request are issued at the same time in the halt state, process A is executed because the INT0 pin request has higher priority over the basic timer 2 request. When an "RETI" instruction is executed after process A is executed, the program flow returns to the "BR LOOP" instruction of accepted. When a "RETI" instruction is executed after execution of basic timer 2 interrupt handling process B, the "BR LOOP" instruction is executed. #, but the "BR LOOP" instruction is not executed and the basic timer 2 interrupt is 284 PD17068 Caution Specify a NOP instruction, immediately before a HALT instruction which is released when an interrupt request flag (IRQxxx) with the corresponding interrupt enable flag (IPxxx) set, is set. A NOP instruction specified immediately before a HALT instruction generates one-instruction execution time between the IRQxxx manipulation instruction and HALT instruction. In example 1, clearing IRQxxx by executing the CLR1 IRQxxx instruction affects the HALT instruction correctly. In example 2, however, the CLR1 IRQxxx instruction does not affect the HALT instruction and the system does not enter the HALT mode, because a NOP instruction is not placed immediately before the HALT instruction. Example 1. Program which correctly executes the HALT instruction ...... ; Sets IRQxxx. CLR1 NOP HALT ... ... IRQxxx ; Places a NOP instruction before the HALT instruction. ; (Clearing IRQxxx correctly affects the HALT instruction.) 1000B ; Executes the HALT instruction correctly (enters the HALT ; mode). ... 2. Program which does not correctly execute the HALT instruction ...... ; Sets IRQxxx. CLR1 HALT ... ... IRQxxx 1000B ; Clearing IRQxxx does not affect the HALT instruction. ; (It affects the instruction after the HALT instruction.) ; Ignores the HALT instruction (does not enter the HALT ; mode). ... 285 PD17068 19.2.7 When Multiple Release Conditions Set Simultaneously When multiple halt release conditions are set, the halt state is released if even one of the set release conditions is satisfied. The following example indicates how to judge multiple release conditions when they are satisfied. Example 1 HLTINT HLTTMR HLTKEY INT0PIN START : BR ORG INT0PIN Process A EI RETI TMRUP : Process B RET KEYDEC : Process C RET MAIN : SET1 SET2 P0C0 BTMCK1, BTMCK0 ; Sets key source output data (high level) at key ; source pin (P0C0). ; Built-in macro ; Sets the cycle of the carry flip-flop of the basic ; timer 0 to 1 ms. SET1 EI LOOP : HALT HLTINT OR HLTTMR OR HLTKEY ; Sets halt release conditions to interrupt, basic ; timer 0 carry, and key input. SKF1 CALL CALL BTM0CY TMRUP KEYDEC ; Built-in macro ; Detects BTM0CY flag. ; If set (1), executes basic timer 0 carry processing. ; If latched, executes key input processing. (How; ever, if the interrupt handling and timer process; ing periods are long, key scanning must be ; repeated.) BR LOOP IP0 ; Built-in macro ; Enables INT0 pin interrupt. ; Key input processing ; Timer carry processing ; INT0 interrupt handling MAIN DAT 1000B DAT 0010B DAT 0001B DAT 000AH ; INT0 interrupt vector address symbol definition 286 PD17068 19.3 CLOCK-STOP FUNCTION The clock-stop function stops the 8 MHz crystal oscillation circuit (clock stopped state) by executing a "STOP s" instruction. The supply current is reduced by up to 15 A. Specify "0000B" at operand "s" of the "STOP s" instruction. The "STOP s" instruction is valid only when the CE pin is low level. If a "STOP s" instruction is executed while the CE pin is high level, it is executed as a "NOP" instruction. Always execute a "STOP s" instruction when the CE pin is low level. The clock-stop state is released by raising the CE pin from low level to high level (CE reset). 19.3.1 Clock-Stop State Since the crystal oscillation circuit is stopped in the clock-stop state, operation of the CPU, peripheral hardware, and other devices is stopped. For a description of operation of the CPU and each item of peripheral hardware, see Section 19.4. In the clock-stop state, the power failure detection circuit does not operate even if the power supply voltage VDD drops to 2.2 V. Data memory can be backed up with a low voltage. For a description of the power failure detection circuit, see Section 20. 19.3.2 Clock-Stop State Release The clock-stop state can be released with the three methods described below. For all three methods, after the clock-stop state is released, the program starts from address 0000H. # $ % set. 19.3.3 Raising the CE pin from low level to high level (CE reset) Raising the P1B2/RLSSTP pin from low level to high level Dropping VDD to 2.2 V or less, then raising it to 4.5 V (power-on reset) To use the P1B2/RLSSTP pin to release the clock-stop state, the RLSEN flag of the control register must be Clock-Stop Release by CE Reset Fig. 19-3 shows the clock-stop release by CE reset. 287 PD17068 Fig. 19-3 Clock-Stop Release by CE Reset 5V VDD 0V H CE pin L H XOUT pin L Approx. 50 ms STOP s instruction Program starts at address 0 (CE reset) 5V VDD 0V H CE pin L H XOUT pin L If a clock-stop instruction is not used, operation is as follows: 0-tSET Program starts at address 0 (CE reset) CE reset is applied in synchronization with the setting of the timer carry flip-flop after the CE pin has been raised to high level. 19.3.4 Clock-Stop Release by Power-On Reset Fig. 19-4 shows the clock-stop release by power-on reset. If the clock-stop state is released by power-on reset, the power failure detection circuit operates. Fig. 19-4 Clock-Stop Release by Power-On Reset 5V VDD 0V H CE pin L H XOUT pin L Approx. 50 ms STOP s instruction Program starts at address 0 (power-on reset) 2.2 V If a clock-stop instruction is not used, operation is as follows: 5V VDD 0V H CE pin L H XOUT pin L Approx. 50 ms Oscillation stopped Program starts at address 0 (power-on reset) 3.5 V 288 PD17068 19.3.5 Clock-Stop Release by R1B2/RLSSTP Pin When the stop-clock state is released by the P1B2/RLSSTP pin, the RLSEN flag of the clock-stop release enable register must be set. The rising edge of the P1B2/RLSSTP pin input can be detected by monitoring the P1B2EDET flag of the P1B2 pin edge detection register. Fig. 19-5 shows the organization and functions of the clock-stop release enable register. Fig. 19-6 shows the organization and functions of the P1B2 pin edge detection register. Fig. 19-5 Configuration of Clock-Stop Release Enable Register Flag symbol Register b3 b2 b1 b0 R L S E N Address Read/write Clock-stop release enable register 0 0 0 20H R/W Sets clock-stop release by P1B2/RLSSTP pin. 0 1 Do not release. Release at rising edge of signal. Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 Hold Hold 289 PD17068 Fig. 19-6 Configuration of P1B2 Pin Edge Detection Register Flag symbol Register b3 b2 b1 b0 P 1 B 2 E D E T Address Read/write P1B2 pin edge detection register 0 0 0 34H R & Reset Detects the rising edge input to the P1B2/RLSSTP pin. 0 1 Rising edge not input. Rising edge input. Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 290 PD17068 19.3.6 Cautions When Using Clock-Stop Instruction The clock-stop instruction (STOP s instruction) is valid only when the CE pin is low level. The program must take into account processing when the CE pin is raised unexpectedly to high level. The description is based on the following example. Example XTAL CEJDG : ; DAT 0000B ; Clock-stop condition symbol definition # SKF1 BR CE MAIN ; Built-in Macro ; Detects the CE pin input level. ; If CE = high level, branches to main processing. ; CE = low level processing $ STOP ;% ; BR MAIN : BR Process A XTAL $-1 ; Clock-stop Main processing CEJDG #. If the CE pin is low level, after process A $ is executed. However, if the CE pin becomes high level while the "STOP XTAL" instruction of $ is being executed as shown in the figure below, the "STOP XTAL" instruction operates as a no operation instruction (NOP). If the branch instruction "BR $-1" of % does not exit, the program returns to main processing and erroneous operational occurs. Therefore, a branch instruction like % must be inserted in the program, or the program must be written so that erroneous operational does not occur even if it returns to main processing. When a branch instruction like % is used, CE reset is applied in synchronization with the next setting of In the example above, the state of the CE pin is detected at is executed, the clock-stop instruction "STOP XTAL" of the carry flip-flop of basic timer 0, even if the CE pin remains at high level. 5V VDD 0V H CE pin L Main processing Process A CE pin detection ### $ STOP XTAL The STOP XTAL becomes a NOP instruction because the CE pin is high level. The program starts from address 0 in synchronization with setting of the carry flipflop of basic timer 0. (CE reset) 291 PD17068 19.4 DEVICE OPERATION AT HALT AND CLOCK-STOP Table 19-1 shows the operation of the CPU and peripheral hardware in the halt state and clock-stop state. In the halt state, all the peripheral hardware units continue to operate normally except that they stop executing instructions. In the clock-stop state, all the peripheral hardware units stop operating. In the halt state, the control register that controls the operating state of the peripheral hardware operates normally (not initialized). However, when a clock-stop instruction is executed, it is initialized to the specified value. In short, in the halt state, the operation set in the control register continues and in the clock-stop state, the operating state is determined in accordance with the initialized control register value. For the control register value in the clock-stop state, see Section 8. A sample program is shown below. Example Program that specifies the P0A0/SDA and P0A1/SCL pins as input ports and uses the P0A2/SCK0 and P0A3/SO0 pins as a serial interface. HLTINT XTAL ; DAT DAT 1000B 0000B # $ INITFLG SET2 INITFLG SET2 INITFLG CLR1 SET1 P0ABIO3, P0ABIO2, P0ABIO1, P0ABIO0 P0A1, P0A0 SIO0CH, NOT SB, SIO0MS, SIO0TX SIO0CK1, SIOCK0 NOT SIO0IMD1, SIO0IMD0 IRQSIO0 IPSIO0 ; % SET1 ;& HALT ;( ; STOP In the example, and EI SIO0NWT HLTINT XTAL # outputs high level from the P0A1 and P0A0 pins, $ sets the serial interface 0 conditions, % starts serial communication. When the HALT instruction is executed at & , serial communication continues, and the halt state is released when a serial interface 0 interrupt is received. If the STOP instruction of ( is executed instead of the HALT instruction of &, all the flags of the control register set at #, $ and % are initialized. Serial communication is terminated and all the port 0A pins are made general-purpose input ports. 292 PD17068 Table 19-1 Device Operation in Halt State and Clock-Stop State State Peripheral hardware CE pin: High level At halt Program counter Stopped at HALT instruction address. Held Held Held Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation STOP instruction invalid (NOP) Normal operation STOP instruction invalid (NOP) At clock-stop CE pin: Low level At halt Stopped at HALT instruction address. Held Held Held Normal operation Normal operation Disabled Normal operation Normal operation Normal operation Operation stopped Normal operation Normal operation Normal operation Normal operation At clock-stop Initialized to 0000H and stopped. InitializedNote Held InitializedNote Operation stopped Normal operation Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Input port Input port Held System register Peripheral register Control register Timers other than watchdog timer Watchdog timer PLL frequency synthesizer A/D converter D/A converter Serial interface IDC Horizontal synchronizing signal counter General-purpose I/O port General-purpose input port General-purpose output port Note For the value that is initialized, see Sections 5 and 8. 19.5 PIN PROCESSING CAUTIONS IN HALT STATE AND CLOCK-STOP STATE The halt state is used to reduce the supply current when only the clock is operating. The clock-stop function is used to reduce the supply current for holding only the data memory. Consequently, the supply current must be reduced as much as possible in the halt and clock-stop states. The supply current depends on the state of each pin and the cautions shown in Table 19-2 must be observed. 293 PD17068 Table 19-2 State of Each Pin and Cautions in Halt and Clock-Stop States (1/2) State of each pin and processing cautions Pin function Port 0A Pin symbol P0A3/SO0 P0A2/SCK0 P0A1/SCL P0A0/SDA P0B3/HSCNT P0B2/I P0B1 P0B0/SI0 P1B3/TMIN P1B2/RLSSTP P1B1/CKOUT P1B0 P1C3 P1C2/ADC7 P1C1/ADC6 P1C0/ADC5 P2D2/SI1 P2D1/SO1 P2D0/SCK1 P0D3/ADC4 P0D2/ADC3 P0D1/ADC2/XTIN P0D0/ADC1/XTOUT P0C3 P0C2 P0C1 P0C0 P1A3 P1A2 P1A1 P1A0 P1D3 P1D2 P1D1 P1D0 P2A0/PWM8 P2B3/PWM7 P2B2/PWM6 P2B1/PWM5 P2B0/PWM4 P2C3/PWM3 P2C2/PWM2 P2C1/PWM1 P2C0/PWM0 Output ports. The output contents are held. If externally pulled down while high level is being output or if externally pulled up while low level is being output, the supply current increases. Halt state The state before halt is held. (1) When specified as output pins If externally pulled down while high level is being output or if externally pulled up while low level is being output, the supply current increases. (2) When specified as input pins When floating, noise, etc. increase the drain current. (3) Port 0D Since a pull-down resistor is built in, when externally pulled up, the drain current increases. Clock-stop state All pins are specified as generalpurpose input pins. Port 0D is internally pulled down. Port 0B General-purpose I/O port General-purpose input port Port 1B Port 1C Port 2D Port 0D Port 0C Port 1A General-purpose output port Port 1D Port 2A Port 2B Port 2C 294 PD17068 Table 19-2 State of Each Pin and Cautions In Halt and Clock-Stop States (2/2) State of each pin and processing cautions Pin function External interrupt Pin symbol INTNC INT0 VCO EO PSC Halt state Clock-stop state When floating, noise, etc. increase the supply current. PLL frequency synthesizer At PLL operation, the supply current increases. The state when PLL is disabled is shown below. VCO : Pulled down internally EO : Floating PSC : Low level output When the CE pin becomes low level, the PLL is automatically disabled. The state before halt is held. PLL disabled state. VCO : Pulled down internally EO : Floating PSC : Low level output Image display controller (IDC) RED GREEN BLUE BLANK P0B2/I RED GREEN BLUE BLANK P0B2/I Low level output Specified general-purpose input port. Crystal oscillation circuit XIN XOUT The supply current changes with the oscillation waveform of the crystal oscillation circuit. The larger the oscillation amplitude, the lower the supply current. Since the oscillation amplitude is governed by the crystal and load capacitor used, evaluation is necessary. The XIN pin is pulled down internally and the XOUT pin outputs high level. 295 PD17068 19.6 DEVICE OPERATION CONTROL BY CE PIN The CE pin controls the following functions by means of the input level and rising edge of a signal received from the outside: (1) Image display controller (IDC) (2) PLL frequency synthesizer (3) Clock-stop instruction disable/enable (4) Device reset 19.6.1 Image Display Controller (IDC) Operation Control The IDC can operate only when the CE pin is high level. When the CE pin is low level, the oscillation circuit stops automatically. 19.6.2 PLL Frequency Synthesizer Operation Control The PLL frequency synthesizer can operate only when the CE pin is high level. When the CE pin is low level, the VCO pin is pulled down inside the device and the EO pin is floated. For details, see Section 18.5. The PLL frequency synthesizer can be disabled by program even when the CE pin is high level. 19.6.3 Clock-Stop Instruction Disable/Enable Control The clock-stop instruction ("STOP s" instruction) is valid only when the CE pin is low level. If the CE pin is high level, the clock-stop instruction is executed as a no operation instruction (NOP). 19.6.4 Device Reset Reset (CE reset) can be applied to the device by raising the CE pin from low level to high level. Besides CE reset, there is also power-on reset, which is activated when VDD is turned on. For details, see Section 20. 296 PD17068 19.6.5 Signal Input to CE Pin To prevent erroneous operation by noise, the CE pin does not accept signals with a low or high level width of less than 110 to 165 s. The level of the signal input to the CE pin can be detected with the CE flag of the CE pin level judge register (RF address 07H). Fig. 19-7 shows the relationship between input signal and CE flag. Fig. 19-7 Relationship of Signal Input to CE Pin and CE Flag H L 1 0 110 to 165 s 110 to 165 s 110 to 165 s 110 to 165 s CE reset PLL operation enabled IDC operation enabled STOP s instruction invalid (NOP) PLL disabled IDC operation stopped STOP s instruction valid PLL disabled IDC operation stopped STOP s instruction invalid (NOP) CE reset is applied in synchronization with the next setting of the carry flip-flop of basic timer 0. CE pin CE flag 19.6.6 Organization and Functions of CE Pin Level Judge Register The CE pin level judge register monitors the CE pin input signal level. Its organization and functions are shown below. Fig. 19-8 Configuration of CE Pin Level Judge Register Flag symbol Register b3 CE pin level judge register 0 b2 0 b1 0 b0 C E 07H R Address Read/write Monitors the level input at the CE pin. 0 1 Low level input High level input Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 - - - The CE flag also does not change when the CE pin receives signals having a low or high level width of less than 110 to 165 s. 297 PD17068 19.6.7 Organization and Functions of CE Pin Edge Detection Register The CE pin edge detection register detects the rising edge of the signal applied to the CE pin. Its organization and functions are shown below. Fig. 19-9 Configuration of CE Pin Edge Detection Register Flag symbol Register b3 b2 b1 b0 C E E D E T Address Read/write CE pin detection register 0 0 0 02H R & Reset Detects the rising edge input at the CE pin. 0 1 Rising edge not input Rising edge input Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 0 - - Remark The CEEDET flag does not change when the CE pin receives signals having a low or high level width of less than 110 to 165 s. 298 PD17068 20. RESET The reset function is used to initialize device operation. 20.1 RESET BLOCK CONFIGURATION Fig. 20-1 shows the configuration of the reset block. Device reset is divided into reset by turning on VDD (power-on reset or VDD reset), and reset by CE pin (CE reset). The power-on reset block consists of a voltage detection circuit that detects the voltage applied to the VDD pin, a power failure detection circuit, and a reset control circuit. The CE reset block consists of a circuit that detects the rising edge of the signal input to the CE pin, and a reset control circuit. Fig. 20-1 Reset Block Power failure detection block Timer flip-flop block BTM0CY flag read R Q S Basic timer 0 carry disable flip-flop Scaler Selector Basic timer 0 carry XOUT XIN STOP s instruction Reset signal VDD Voltage detection circuit Rising edge detection circuit Power-on clear signal (POC) Reset control circuit IRES RES RESET Forced halt by basic timer 0 carry Control register System register Stack Program counter CE STOP instruction 299 PD17068 20.2 RESET FUNCTION Power-on reset is applied when VDD rises from a certain voltage. CE reset is applied when the CE pin rises from low level to high level. Power-on reset initializes the program counter, stack, system register and control registers, and executes the program from address 0000H. CE reset initializes the program counter, stack, system register and some control registers, and executes the program from address 0000H. The main differences between power-on reset and CE reset are the operation of the control registers that are initialized and the power failure detection circuit described in Section 20.6. Power-on reset and CE reset are controlled by reset signals IRES, RES, and RESET output from the reset control circuit in Fig. 20-1. Table 20-1 shows the IRES, RES, and RESET signal and power-on reset and CE reset relationship. The reset control circuit also operates when the clock-stop instruction (STOP s) described in Section 19 is executed. Sections 20.3 and 20.4 describe CE reset and power-on reset, respectively. Section 20.5 describes the relationship between CE reset and power-on reset. Table 20-1 Relationship Between Internal Reset Signal and Each Reset Output signal Internal reset signal At CE reset x At poweron reset q At clock-stop Contents controlled by each reset signal IRES q Forces the device into the halt state. The halt state is released by the setting of the carry flip-flop of basic timer 0. Initializes some control registers. Initializes the program counter, stack, system register, and some control registers. RES RESET x q q q q q 300 PD17068 20.3 CE RESET CE reset is executed by raising the CE pin from low level to high level. When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the carry flip-flop of basic timer 0. When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some control registers to their initial value and executes the program from address 0000H. For the initial values, see the relevant item. CE reset operation is different when clock-stop is used and when it is not used. These operations are described in Sections 20.3.1 and 20.3.2, respectively. Section 20.3.3 describes the cautions at CE reset. 20.3.1 CE Reset When Clock-Stop (STOP s Instruction) Not Used Fig. 20-2 shows the reset operation. When clock-stop (STOP s instruction) is not used, the basic timer 0 clock selection register of the control registers is not initialized. Therefore, after the CE pin becomes high level, the RESET signal is output, and reset is applied at the rising edge of the selected pulse (1 ms, 5 ms, or 100 ms) used for setting the carry flip-flop of basic timer 0. Fig. 20-2 CE Reset Operation When Clock-Stop Not Used 5V VDD CE L H XOUT Pulse used for setting the carry flip-flop of basic timer 0. IRES RES RESET L H L H L H L H L Normal operation Normal operation 0V H Reset signal CE reset is applied at the rising edge of the pulse used for setting the carry flip-flop of basic timer 0. This period, t, varies with the timing when the CE pin signal rises. It falls in the range from 0 to tSET (0 < t < tSET), which is the selected set time of the carry flip-flop of basic timer 0. The program continues to run during this period. 301 PD17068 20.3.2 CE Reset When Clock-Stop (STOP s Instruction) Used Fig. 20-3 shows the reset operation. When clock-stop is used, the IRES, RES and RESET signals are output at the time the "STOP s" instruction is executed. At this time, the RES signal initializes the basic timer 0 clock selection register of the control registers to 0000B and sets the basic timer 0 carry flip-flop setting signal to 100 ms. Since the IRES signal is output continuously while the CE pin is low level, release by basic timer 0 carry is forcibly halted. Since the clock itself stops, the device stops operating. When the CE pin rises to high level, the clock-stop state is released and oscillation begins. The IRES signal halts release by basic timer 0 carry. When the pulse used for setting the carry flip-flop of basic timer 0 rises after the CE pin rises, the halt state is released and the program starts from address 0. Since the basic timer 0 carry flip-flop setting pulse is initialized to 100 ms, CE reset is applied 50 ms after the CE pin rises to high level. Fig. 20-3 CE Reset Operation When Clock-Stop Used 5V VDD CE L H XOUT Basic timer 0 carry flip-flop setting pulse IRES RES RESET L H L H L H L H L Normal operation Clock-stop state Halt state 50 ms CE reset Program starts from address 0. 0V H Reset signal STOP s instruction Clock stop release Oscillation start 302 PD17068 20.3.3 Cautions at CE Reset When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) Time required for clock and other timer processing When writing a clock program by using basic timer 0 carry and basic timer 2 interrupts, the program must end processing within a certain time. For details, see Sections 12.2.6 and 12.4.5. (2) Processing of data, flags, etc. used in the program Care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one instruction so that the contents do not change even when CE reset is applied. 303 PD17068 20.4 POWER-ON RESET Power-on reset is executed by raising VDD from a certain voltage (called the power-on clear voltage) or less. When VDD is less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage detection circuit shown in Fig. 20-1. When the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating. While the power-on clear signal is being output, the IRES, RES and RESET signals are output. When VDD exceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation starts. At the same time, the IRES, RES and RESET signals are also dropped. Since the IRES signal halts release by basic timer 0 carry, power-on reset is applied at the rising edge of the next basic timer 0 carry flip-flop setting signal. Since the RESET signal has initialized the basic timer 0 carry flip-flop setting signal to 100 ms, 50 ms after VDD exceeds the power-on clear voltage, reset is applied and the program starts from address 0. This operation is shown in Fig. 20-4. At power-on reset, the program counter, stack, system register and control registers are initialized when the power-on clear signal is output. For the initial values, see the relevant items. During normal operation, the power-on clear voltage is 3.5 V (rated value). In the clock-stop state, the power-on clear voltage becomes 2.2 V (rated value). Sections 20.4.1 and 20.4.2 describe operation at this time. Section 20.4.3 describes operation when VDD rises from 0 V, Fig. 20.4 Power-On Reset Operation 5V VDD CE L H XOUT Basic timer 0 carry flip-flop setting pulse Power-on clear signal IRES RES RESET L H L H L H L H L H L Normal operation Device operation stopped Halt state 50 ms Power-on reset Program starts from address 0 Power-on clear voltage 0V H Reset signal Power-on clear release Oscillation start 304 PD17068 20.4.1 Power-On Reset at Normal Operation Fig. 20-5 (a) shows power-on reset at normal operation. As shown in Fig. 20-5 (a), when the VDD drops below 3.5 V, the power-on clear signal is output and operation of the device stops regardless of the input level of the CE pin. When VDD then rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H. Normal operation refers to the state in which the clock-stop instruction is not used. This also includes the halt state set by the halt instruction. 20.4.2 Power-On Reset in Clock-Stop State Fig. 20-5 (b) shows power-on reset in the clock-stop state. As shown in Fig. 20-5 (b), when VDD drops below 2.2 V, the power-on clear signal is output and device operation stops. However, since the device is in the clock-stop state, its operation apparently does not change. When VDD rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H. 20.4.3 Power-On Reset When VDD Rises From 0 V Fig. 20-5 (c) shows power-on reset when VDD rises from 0 V. As shown in Fig. 20-5 (c), the power-on clear signal is being output while VDD is rising from 0 V to 3.5 V. When VDD rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 50 ms halt, the program starts from address 0000H. 305 PD17068 Fig. 20-5 Power-On Reset and VDD (a) During normal operation (including halt state) 5V 3.5 V VDD 0V H CE L H XOUT Power-on clear signal L H L Normal operation Device operation stopped Power-on clear voltage Halt state 50 ms Power-on reset Program starts from address 0 Power-on clear release Oscillation start (b) At clock-stop 5V 3.5 V VDD 0V H CE L H XOUT Power-on clear signal L H L Normal operation Device operation stopped 2.2 V Power-on clear voltage Clock-stop Halt state 50 ms Power-on reset Program starts from address 0 STOP s instruction Power-on clear release Oscillation start (c) When VDD rises from 0 V 5V 3.5 V VDD 0V H CE L H XOUT Power-on clear signal L H L Device operation stopped Halt state 50 ms Power-on clear release Power-on reset Oscillation start Program starts from address 0 Power-on clear voltage 306 PD17068 20.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When VDD is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 20.5.1 through 20.5.3 describe this reset operation. Section 20.5.4 describes the cautions when VDD rises. 20.5.1 When VDD Pin and CE Pin Rise Simultaneously Fig. 20-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H. 20.5.2 20.5.1. 20.5.3 When CE Pin Raised After Power-On Reset When CE Pin Raised in Forced Halt State Caused by Power-On Reset. Fig. 20-6 (b) shows the reset operation. Power-on reset starts the program from address 0000H, as in Section Fig. 20-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset restarts the program from address 0000H at the rising edge of the next basic timer 0 carry flip-flop setting signal. 307 PD17068 Fig. 20-6 Relationship Between Power-On Reset and CE Reset (a) When VDD and CE pin raised simultaneously 5V 3.5 V VDD 0V H CE L Basic timer 0 carry flip-flop setting pulse H L Operation stopped Power-on clear voltage Halt state 50ms Normal operation Power-on reset Program start (b) When CE Pin Raised in Halt State 5V 3.5 V VDD 0V H CE L Basic timer 0 carry flip-flop setting pulse H L Operation stopped Power-on clear voltage Halt state 50 ms Normal operation Power-on reset Program start (c) When CE Pin Raised After Power-On Reset 5V 3.5 V VDD 0V H CE L Basic timer 0 carry flip-flop setting pulse H L Operation stopped Power-on clear voltage Halt state 50 ms Normal operation CE reset Program start Power-on reset Program start 308 PD17068 20.5.4 Cautions When VDD Raised When VDD is raised, careful attention must be given to points (1) and (2) below. (1) When VDD raised from power-on clear voltage When VDD is raised, it must raised to 3.5 V or greater, once. This is shown in Fig. 20-7. As shown in Fig. 20-7, when a voltage under 3.5 V is applied when VDD is turned on in a program that uses clock-stop to back up VDD at 2.2 V, for example, the power-on clear signal continues to be output and the program does not run. Since the device output port outputs an undefined value, the supply current increases, according to the situation, reducing the back-up time with a battery considerably. Fig. 20-7 Caution When VDD Raised 5V 3.5 V VDD 2.2 V 0V H CE L H XOUT L H L H L Operation stopped Since the values of the output ports, etc. are undefined during this period, the supply current may increase. Operation stopped Power-on clear voltage Basic timer 0 carry flip-flop setting pulse Power-on clear signal Halt state 50 ms Normal operation During this period, initialization is performed, then the clock is stopped. Back-up Power-on reset Program start STOP s instruction 309 PD17068 (2) At return from clock-stop state When returning from the back-up state when clock-stop is used to back-up VDD at 2.2 V, VDD must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level. As shown in Fig. 20-8, return from the clock-stop state is performed by CE reset. Since the power-on clear voltage is switched to 3.5 V 50 ms after the CE pin is raised, if VDD is not 3.5 V or greater at this time, poweron reset is applied. The same caution is necessary when VDD is dropped. Fig. 20-8 Return From Clock-Stop State 5V VDD 0V H CE L H XOUT L H L H L Back-up caused by clock stop Halt state 50 ms Normal operation CE=low processing Back-up 3.5 V 2.2 V Power-on clear voltage Basic timer 0 carry flip-flop setting pulse Power-on clear signal CE reset Program start STOP s instruction At this point, the power-on clear voltage is switched to 3.5 V. Therefore, VDD must be raised to 3.5 V or greater before this point. At this point, the power-on clear voltage is switched to 2.2 V. Therefore, VDD must not be dropped below 3.5 V before this point. 310 PD17068 20.6 POWER FAILURE DETECTION Power failure detection is used to judge whether the device is reset by turning on VDD or by the CE pin, as shown in Fig. 20-9. Since the contents of the data memory, output ports, etc. become "undefined" when VDD is turned on, they are initialized by power failure detection. There are two power failure detection methods. One method detects a power failure by using a power failure detection circuit to detect the BTM0CY flag and the other method detects the contents of the data memory (RAM judgment). Sections 20.6.1 and 20.6.2 describe the power failure detection circuit, and power failure detection by BTM0CY flag, respectively. Sections 20.6.3 and 20.6.4 describe power failure detection with the RAM judgment method. Fig. 20-9 Power Failure Detection Flowchart Program start Power failure detection Power failure No power failure Data memory, output port, etc. initialization 20.6.1 Power Failure Detection Circuit As shown in Fig. 20-1, the power failure detection circuit consists of a voltage detection circuit and timer carry disable flip-flop that is reset by the output (power-on clear signal) of the voltage detection circuit, and basic timer 0 carry. The basic timer 0 carry disable flip-flop is set (1) by the power-on clear signal and is reset (0) when a BTM0CY flag read instruction is executed. When the basic timer 0 carry disable flip-flop is set (1), the BTM0CY flag is not set (1). That is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which the BTM0CY flag is reset and the setting disabled state is set until a BTM0CY read instruction is executed thereafter. Once a BTM0CY read instruction is executed, the BTM0CY flag is set at each rising edge of the basic timer 0 carry flip-flop setting pulse thereafter. When reset is applied to the device, the contents of the BTM0CY flag are monitored. If the BTM0CY flag has been reset (0), power-on reset (power failure) is judged and if the BTM0CY flag has been set (1), CE reset (no power failure) is judged. Since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, VDD becomes 3.5 V at crystal oscillation and 2.2 V at clock-stop. Fig. 20-10 shows the BTM0CY flag state transition. Fig. 20-11 shows timing chart and BTM0CY flag operation specified in Fig. 20-10. 311 PD17068 Fig. 20-10 BTM0CY Flag State Transition CE = low # $ CE = optional VDD = low Operation stopped CE = high VDD = L3.5 V Crystal oscillation start Forced halt (approx. 50 ms) BTM0CY flag setting disabled state Power-on reset & Clock-stop STOP0 ( CE = 1 Normal operation CE = HL ) CE = H Normal operation BTM0CY = 0 * CE = LH + CE reset Rising edge of basic timer 0 carry flip-flop setting pulse - SKT1 BTM0CY or SKF1 BTM0CY CE = LH , Normal operation CE set wait SKT1 BTM0CY or SKF1 BTM0CY . Crystal oscillation start Forced halt (50 ms) / Clock-stop BTM0CY flag setting enable state STOP0 0 Normal operation CE = HL 1 Normal operation CE = LH 3 BTM0CY = 1 2 CE reset Rising edge of basic timer 0 carry flip-flop setting pulse CE = LH 4 Normal operation CE set wait Crystal oscillation start Forced halt (50 ms) 312 PD17068 Fig. 20-11 BTM0CY Flag Operation (a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed) 5V VDD CE Basic timer 0 carry flip-flop setting pulse BTM0CY Fig. 20-10 operation 0V H L H L H L #$) % ( Timer time switching + * ) ( &, STOP 0000 B ) * # (b) When power failure detected with BTM0CY flag 5V VDD CE Basic timer 0 carry flip-flop setting pulse BTM0CY SKT1 instruction Fig. 20-10 operation 0V H L H L H L # $ )1 %. 0 Timer time switching 3 2 1 0 /4 STOP 0000 B 1 2 BTM0CY=1 No power failure # BTM0CY=0 Power failure BTM0CY=1 No power failure 313 PD17068 20.6.2 Cautions at Power Failure Detection with BTM0CY Flag When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points. (1) Clock updating When writing a clock program by using basic timer 0, the clock must be updated after a power failure. This is because the BTM0CY flag is reset (0) and one clock count is lost by BTM0CY flag reading when a power failure is detected. (2) Clock update processing time When the clock is updated, its processing must end before the next rising edge of the basic timer 0 flipflop setting pulse. This is because if the CE pin rises to high level during clock update processing, the clock update processing will not be executed up to the end and a CE reset will be applied. For (1) and (2) above, see Section 12.2.6 (3). When processing is performed at a power failure, careful attention must be given to the following point. (3) Power failure detection timing When clock counting, etc. is performed with the BTM0CY flag, the flag must be read for power-failure detection before the next rising edge of the basic timer 0 carry flip-flop setting pulse, after a program starts from address 0000H. This is because when the basic timer 0 carry flip-flop setting time is set to 5 ms, for instance, and power failure detection is performed 6 ms after the program starts, one BTM0CY flag is lost. See Section "12.2.6 (3). As shown in the example on the next page, power failure detection and initialization must be performed within the basic timer 0 carry flip-flop set time. This is because when the CE pin is raised and CE reset is applied during power failure processing and initialization, these processings are interrupted and a problem may occur. When the basic timer 0 carry flip-flop set time is changed in initialization, an instruction that makes the change must be executed at the end of initialization. This is also because when the basic timer 0 carry flip-flop set time is switched before initialization as shown in the example on the next page, initialization by CE reset may not be executed up to the end. 314 PD17068 Example Sample program START: ; # $ % ; Program address 0000H Reset processing SKT1 BR BTM0CY INITIAL ; Power failure detection ; BACKUP: ; Clock updating BR INITIAL: MAIN & ;( ; Initialization INITFLG NOT BTM0CK1, BTM0CK0 ; Built-in macro ; Sets basic timer 0 carry flip-flop set time to 5 ms. MAIN: Main process SKT1 BR BTM0CY MAIN Clock updating BR Operation example MAIN VDD CE 5V 0V H L 50 ms 50 ms Basic timer 0 carry flip-flop setting pulse H L # Power failure detection When the processing time of + is 100 ms or longer, a CE reset is applied midway through processing 4. $ #& & $ Power failure detection When the processing time ( of # + % is too long, a CE reset is applied. CE reset CE reset # % CE reset may be applied immediately, depending on the basic timer 0 carry flip-flop set time switching timing. When is executed before power failure processing may not be executed up to the end. & ( &, 315 PD17068 20.6.3 Power Failure Detection by RAM Judgment The RAM judgment method detects a power failure by judging if the contents of the data memory at a specified address are the specified value when the device was reset. A sample program that detects a power failure by RAM judgment is shown on the next page. The contents of data memory when VDD is turned on are "undefined". The RAM judgment method performs power failure detection by comparing the "undefined value" with the "specified value". Therefore, power failure detection may be judged erroneously, as described in Section 20.6.4. However, the advantage of using the RAM judgment method is that, as shown in Table 20-2, back-up down to a lower voltage than that detected by power detection circuit is possible. Table 20-2 Comparison of Power Failure Judgment Circuit and Power Failure Detection by RAM Judgment Power failure detection circuit Data hold voltage (at clock-stop) Remarks Actual value 2 - 2.2 V Rating 2.2 V RAM judgment Actual value 0-1V Rating 2.2 V No erroneous operation Erroneous operation possible 316 PD17068 Sample program which detects power failure by RAM judgment M012 M034 M056 M107 M128 M16F DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 START: SET2 SUB SUB SUB BANK1 SUB SUB SUB BANK0 SKF1 BR ; INITIAL: Initialization MOV MOV MOV BANK1 MOV MOV MOV BR BACKUP: Back-up processing MAIN: Main processing M107, #DATA3 M128, #DATA4 M16F, #DATA5 MAIN M012, #DATA0 M034, #DATA1 M056, #DATA2 Z BACKUP ; Branches to BACKUP M107, #DATA3 ; M107 = DATA3 and M128, #DATA4 ; M128 = DATA4 and M16F, #DATA5 ; M16F = DATA5 CMP, Z M012, #DATA0 ; If M012 = DATA0 and M034, #DATA1 ; M034 = DATA1 and M056, #DATA2 ; M056 = DATA2 and MEM MEM MEM MEM MEM MEM DAT DAT DAT DAT DAT DAT 0.12H 0.34H 0.56H 1.07H 1.28H 1.6FH 1010B 0101B 0110B 1001B 1100B 0011B 317 PD17068 20.6.4 Cautions at Power Failure Detection by RAM Judgment Since the data memory value when VDD is turned on is "undefined", careful attention must be given to points (1) and (2) below. (1) Comparison data When n bits of data memory is to be compared by RAM judgment, the probability that the data memory value when VDD is turned on may unexpectedly match the specified value is (1/2)n. That is, there is a (1/2)n probability that power failure detection by RAM judgment will be judged backup. To reduce this probability, the largest number of bits possible are compared. Since, from experience, the contents of data memory when VDD is turned on easily becomes the same value, such as "0000B" and "1111B", comparison data that mixes "0" and "1", such as "1010B" and "0110B", reduces the possibility of erroneous judgment. (2) Program cautions When VDD is raised from a voltage that begins to destroy the data memory as shown in Fig. 20-12, even if the value of data memory to be compared is normal, other values may be destroyed. Since power failure detection by RAM judgment judges it as back-up, the program must be written so that it does not crash even if the data memory is destroyed. Fig. 20-12 VDD and Destruction of Data Memory 5V VDD Data memory destruction start voltage 0V Data memory RAM judgment data memory (normal) The value of the data memory not used in RAM judgment may be destroyed. 318 PD17068 21. INSTRUCTION SET 21.1 LIST OF INSTRUCTION SET b15 b14-b11 BIN 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 HEX 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL SYSCAL RET RETSK EI DI RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP LD SKE MOV SKNE BR BR BR BR r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR entry ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1 0 1 1 1 7 AR AR DBF, p p, DBF WR, rf rf, WR r s h 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 A B C D E F r, m m, #n4 @r, m m, #n4 addr (PAGE 0) addr (PAGE 1) addr (PAGE 2) addr (PAGE 3) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr (PAGE 0) m, #n4 m, #n m, #n 319 PD17068 21.2 Legend AR ASR addr BANK CMP CY DBF entry entryH entryL h INTEF INTR INTSK IX MP MPE m mR mC n n4 PAGE PC p pH pL r rf rfR rfC SGR SP s WR (x) : Address register : Address stack register pointed to by the stack pointer : Program memory address (11 low-order bits) : Bank register : Compare flag : Carry flag : Data buffer : Program memory address (bits 10 to 8, bits 3 to 0) : Program memory address (bits 10 to 8) : Program memory address (bits 3 to 0) : Halt release condition : Interrupt enable flag : Register automatically saved in the stack when an interrupt occurs : Interrupt stack register : Index register : Data memory row address pointer : Memory pointer enable flag : Data memory address specified by mR and mC : Data memory row address (high-order) : Data memory column address (low-order) : Bit position (four bits) : Immediate data (four bits) : Page (Bits 12 and 11 of the program counter) : Program counter : Peripheral address : Peripheral address (three high-order bits) : Peripheral address (four low-order bits) : General register column address : Register file address : Register file address (three high-order bits) : Register file address (four low-order bits) : Segment register (Bit 13 of the program counter) : Stack pointer : Stop release condition : Window register : Contents of x INSTRUCTIONS 320 PD17068 Instruction set Add Mnemonic ADD Instruction code Operand r, m m, #n4 ADDC r, m m, #n4 INC AR IX Subtract SUB r, m m, #n4 SUBC r, m m, #n4 Logical operation OR r, m m, #n4 AND r, m m, #n4 XOR r, m m, #n4 Test SKT SKF Compare SKE SKNE SKGE SKLT Rotation RORC m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 CMP 0, if (m) n = n, then skip CMP 0, if (m) n = 0, then skip (m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0 (r) (m) (m) (r) if MPE = 1: (MP, (r)) (m) if MPE = 0: (BANK, mR, (r)) (m) if MPE = 1: (m) (MP, (r)) if MPE = 0: (m) (BANK, mR, (r)) (m) n4 SP SP - 1, ASR PC, PC AR, DBF (PC), PC ASR, SP SP + 1 Operation Op code 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r Transfer LD ST MOV r, m m, r @r, m 01000 11000 01010 mR mR mR mC mC mC r r r m, @r 11010 mR mC r m, #n4 MOVT DBF, @AR 11101 00111 mR 000 mC 0001 n4 0000 321 PD17068 Instruction set Transfer Mnemonic PUSH POP PEEK POKE GET PUT Branch BR Instruction code Operand AR AR WR, rf rf, WR DBF, p p, DBF addr Operation SP SP - 1, ASR AR AR ASR, SP SP + 1 WR (rf) (rf) WR DBF (p) (p) DBF PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 PC10-0 addr, PAGE 3 @AR Subroutine CALL addr PC AR SP SP - 1, ASR PC, PC12,11 0, PC10-0 addr SP SP - 1, ASR PC, PC AR SP SP - 1, ASR PC, SGR 1, PC12,11 0, PC10-8 entryH, PC 7-4 0, PC3-0 entryL PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0 s h STOP HALT No operation Op code 00111 00111 00111 00111 00111 00111 01100 01101 01110 01111 00111 11100 000 0100 addr 0000 000 000 rfR rfR pH pH Operand 1101 1100 0011 0010 1011 1010 addr 0000 0000 rfC rfC pL pL @AR 00111 000 0101 0000 SYSCAL entry 00111 entryH 0000 entryL RET RETSK RETI Interrupt EI DI Others STOP HALT NOP 00111 00111 00111 00111 00111 00111 00111 00111 000 000 100 000 001 010 011 100 0101 1110 1110 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 s h 0000 322 PD17068 21.3 ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS Legend flag n <> : FLG-type symbol : An operand enclosed in < > is optional. Mnemonic Built-in macro SKTn SKFn SETn CLRn NOTn Operand flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n ) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n ) 0 if description = flag n, then (flag n) 1 (BANK) n n 1n4 1n4 1n4 1n4 1n4 1n4 0n2 INITFLG BANKn 323 PD17068 22. RESERVED SYMBOLS 22.1 DATA BUFFER (DBF) Symbol DBF3 DBF2 DBF1 DBF0 Attribute MEM MEM MEM MEM Value 0.0CH 0.0DH 0.0EH 0.0FH Read/ write R/W R/W R/W R/W DBF bits 15 to 12 DBF bits 11 to 8 DBF bits 7 to 4 DBF bits 3 to 0 Description 22.2 SYSTEM REGISTER (SYSREG) Symbol AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE Attribute MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG Value 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15 to 12 of the address register Bits 11 to 8 of the address register Bits 7 to 4 of the address register Bits 3 to 0 of the address register Window register Bank register Index register high Memory pointer high Memory pointer enable flag Index register middle Memory pointer low Index register low General register pointer high General register pointer low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag 22.3 VRAM BANK REGISTER Symbol VRAMBANK Attribute MEM Value 2.73H Read/ write R/W VRAM bank register Description 324 PD17068 22.4 PORT REGISTER Symbol P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 P1C3 P1C2 P1C1 P1C0 P1D3 P1D2 P1D1 P1D0 P2A0 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.70H.3 0.70H.2 0.70H.1 0.70H.0 0.71H.3 0.71H.2 0.71H.1 0.71H.0 0.72H.3 0.72H.2 0.72H.1 0.72H.0 0.73H.3 0.73H.2 0.73H.1 0.73H.0 1.70H.3 1.70H.2 1.70H.1 1.70H.0 1.71H.3 1.71H.2 1.71H.1 1.71H.0 1.72H.3 1.72H.2 1.72H.1 1.72H.0 1.73H.3 1.73H.2 1.73H.1 1.73H.0 2.70H.0 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 3 of port 0A Bit 2 of port 0A Bit 1 of port 0A Bit 0 of port 0A Bit 3 of port 0B Bit 2 of port 0B Bit 1 of port 0B Bit 0 of port 0B Bit 3 of port 0C Bit 2 of port 0C Bit 1 of port 0C Bit 0 of port 0C Bit 3 of port 0D Bit 2 of port 0D Bit 1 of port 0D Bit 0 of port 0D Bit 3 of port 1A Bit 2 of port 1A Bit 1 of port 1A Bit 0 of port 1A Bit 3 of port 1B Bit 2 of port 1B Bit 1 of port 1B Bit 0 of port 1B Bit 3 of port 1C Bit 2 of port 1C Bit 1 of port 1C Bit 0 of port 1C Bit 3 of port 1D Bit 2 of port 1D Bit 1 of port 1D Bit 0 of port 1D Bit 0 of port 2A Description 325 PD17068 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 3 of port 2B Bit 2 of port 2B Bit 1 of port 2B Bit 0 of port 2B Bit 3 of port 2C Bit 2 of port 2C Bit 1 of port 2C Bit 0 of port 2C Bit 2 of port 2D Bit 1 of port 2D Bit 0 of port 2D Symbol P2B3 P2B2 P2B1 P2B0 P2C3 P2C2 P2C1 P2C0 P2D2 P2D1 P2D0 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 2.71H.3 2.71H.2 2.71H.1 2.71H.0 2.72H.3 2.72H.2 2.72H.1 2.72H.0 2.6FH.2 2.6FH.1 2.6FH.0 Description 326 PD17068 22.5 REGISTER FILES Symbol SP CEEDET PWM8SEL PWM7SEL PWM6SEL PWM5SEL PWM4SEL PWM3SEL PWM2SEL PWM1SEL PWM0SEL WTMHLD CKOSEL XTSEL CE SIO0CH SB SIO0MS SIO0TX TM0CK BTM2EXCK BTM2ZX BTM2CK1 BTM2CK0 BTM1EXCK BTM1ZX BTM1CK1 BTM1CK0 BTM0CK1 BTM0CK0 TM0RPT TM0RES TM0EN TM0OVF Attribute MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.81H 0.82H.0 0.83H.0 0.84H.3 0.84H.2 0.84H.1 0.84H.0 0.85H.3 0.85H.2 0.85H.1 0.85H.0 0.86H.3 0.86H.1 0.86H.0 0.87H.0 0.88H.3 0.88H.2 0.88H.1 0.88H.0 0.89H.0 0.8AH.3 0.8AH.2 0.8AH.1 0.8AH.0 0.8BH.3 0.8BH.2 0.8BH.1 0.8BH.0 0.8CH.1 0.8CH.0 0.8DH.2 0.8DH.1 0.8DH.0 0.8EH.0 Read/ write R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R Stack pointer CE pin edge detection flag PWM8/P2A0 pin selection flag PWM7/P2B3 pin selection flag PWM6/P2B2 pin selection flag PWM5/P2B1 pin selection flag PWM4/P2B0 pin selection flag PWM3/P2C3 pin selection flag PWM2/P2C2 pin selection flag PWM1/P2C1 pin selection flag PWM0/P2C0 pin selection flag Watch timer hold flag P1B1/CKOUT pin selection flag Description Function selection flag of P0D1 and P0D0 pins CE pin status flag SIO0 channel selection flag SIO0 mode selection flag SIO0 clock mode selection flag SIO0 TX/RX selection flag Timer 0 clock selection flag Bit 3 of basic timer 2 clock selection flag Bit 2 of basic timer 2 clock selection flag Bit 1 of basic timer 2 clock selection flag Bit 0 of basic timer 2 clock selection flag Bit 3 of basic timer 1 clock selection flag Bit 2 of basic timer 1 clock selection flag Bit 1 of basic timer 1 clock selection flag Bit 0 of basic timer 1 clock selection flag Bit 1 of basic timer 0 clock selection flag Bit 0 of basic timer 0 clock selection flag Timer 0 mode (repeat) selection flag Timer 0 reset flag Timer 0 start/stop flag Timer 0 overflow detection flag 327 PD17068 Read/ write R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R Symbol IGRP1SL IGRP0SL HSCGT1 HSCGT0 HSCGOSTT PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0 WTMRES3 WTMRES2 WTMRES1 WTMRES0 INTNCMD2 INTNCMD1 INTNCMD0 BTM1CY BTM0CY SBACK SIO0NWT SIO0WRQ1 SIO0WRQ0 SIO0WSTT TM1CK1 TM1CK0 TM1RES TM1EN SIO1TS SIO1HIZ SIO1CK1 SIO1CK0 WTM8HZ WTM128HZ Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.8FH.1 0.8FH.0 0.91H.1 0.91H.0 0.92H.3 0.93H.3 0.93H.2 0.93H.1 0.93H.0 0.94H.3 0.94H.2 0.94H.1 0.94H.0 0.95H.2 0.95H.1 0.95H.0 0.96H.0 0.97H.0 0.98H.3 0.98H.2 0.98H.1 0.98H.0 0.99H.0 0.9AH.1 0.9AH.0 0.9BH.1 0.9BH.0 0.9CH.3 0.9CH.2 0.9CH.1 0.9CH.0 0.9DH.0 0.9EH.0 Description Interrupt request group 1 selection flag Interrupt request group 0 selection flag Bit 1 of HSYNC-counter gate-mode selection flag Bit 0 of HSYNC-counter gate-mode selection flag HSYNC-counter gate open status flag Bit 3 of PLL reference clock selection flag Bit 2 of PLL reference clock selection flag Bit 1 of PLL reference clock selection flag Bit 0 of PLL reference clock selection flag Watch timer (day setting register) reset flag Watch timer (second/minute/hour setting register) reset flag Watch timer (basic clock) reset flag Watch timer (all) reset flag Bit 2 of INTNC pulse width selection flag Bit 1 of INTNC pulse width selection flag Bit 0 of INTNC pulse width selection flag Basic timer 1 carry flag Basic timer 0 carry flag SIO0 acknowledge flag SIO0 not-wait flag Bit 1 of SIO0 wait timing setting flag Bit 0 of SIO0 wait timing setting flag Judge flag of SIO0 wait status Bit 1 of timer 1 clock selection flag Bit 0 of timer 1 clock selection flag Timer 1 reset flag Timer 1 enable flag SIO1 start flag P2D1/SO1 pin selection flag Bit 1 of SIO1 clock selection flag Bit 0 of SIO1 clock selection flag Watch timer 8 Hz carry detection flag Watch timer 128 Hz carry detection flag 328 PD17068 Read/ write R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Symbol IEGGRP1 IEG0 IEGNC RLSEN ADCCH2 ADCCH1 ADCCH0 PLLUL ADCEN ADCCMP P2DBIO2 P2DBIO1 P2DBIO0 P1CGIO SIO0SF8 SIO0SF9 SBSTT SBBSY IRQGRP0 IRQSIO1 IRQSIO0 INTGRP1 IRQGRP1 IPGRP0 IPSIO1 IPSIO0 IPGRP1 IPIDCVP IPBTM2 IPTM1 IPTM0 IP0 IPNC Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.9FH.2 0.9FH.1 0.9FH.0 0.0A0H.0 0.0A1H.2 0.0A1H.1 0.0A1H.0 0.0A2H.0 0.0A4H.3 0.0A4H.0 0.0A6H.2 0.0A6H.1 0.0A6H.0 0.0A7H.0 0.0A8H.3 0.0A8H.2 0.0A8H.1 0.0A8H.0 0.0A9H.0 0.0AAH.0 0.0ABH.0 0.0ACH.3 0.0ACH.0 0.0ADH.1 0.0ADH.0 0.0AEH.3 0.0AEH.2 0.0AEH.1 0.0AEH.0 0.0AFH.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 Description Interrupt group 1 edge detection selection flag INT0 pin interrupt edge detection selection flag INTNC pin interrupt edge detection selection flag Clock stop release setting flag with P1B2 pin Bit 2 of A/D converter channel selection flag Bit 1 of A/D converter channel selection flag Bit 0 of A/D converter channel selection flag PLL unlock flip-flop flag A/D converter enable flag A/D converter comparator output I/O selection flag of P2D2 pin I/O selection flag of P2D1 pin I/O selection flag of P2D0 pin P1C group I/O selection flag SIO0 shift 8 clock flag SIO0 shift 9 clock flag SIO0 start condition detection flag SIO0 busy condition detection flag Interrupt group 0 (TM0OVF signal) interrupt request flag SIO1 interrupt request flag SIO0 interrupt request flag Interrupt group 1 (HSYNC or VSYNC signal) interrupt status flag Interrupt group 1 (HSYNC or VSYNC signal) interrupt request flag Interrupt group 0 (TM0OVF signal) interrupt enable flag SIO1 interrupt enable flag SIO0 interrupt enable flag Interrupt group 1 (HSYNC or VSYNC signal) interrupt enable flag IDC VRAM pointer interrupt enable flag Basic timer 2 interrupt enable flag Timer 1 interrupt enable flag Timer 0 interrupt enable flag INT0 pin interrupt enable flag INTNC pin interrupt enable flag 329 PD17068 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W Symbol IDCBKEN IDCBKR IDCBKG IDCBKB IDCEN PLULSEN1 PLULSEN0 VRAMSEL IDCISEL IDCD14SL IDCCPCH P1B2EDET P1BBIO3 P1BBIO2 P1BBIO1 P1BBIO0 P0BBIO3 P0BBIO2 P0BBIO1 P0BBIO0 P0ABIO3 P0ABIO2 P0ABIO1 P0ABIO0 SIO0IMD1 SIO0IMD0 SIO0CK1 SIO0CK0 IRQIDCVP IRQBTM2 IRQTM1 IRQTM0 INT0 IRQ0 INTNC IRQNC Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.0B0H.3 0.0B0H.2 0.0B0H.1 0.0B0H.0 0.0B1H.0 0.0B2H.1 0.0B2H.0 0.0B3H.3 0.0B3H.2 0.0B3H.1 0.0B3H.0 0.0B4H.0 0.0B5H.3 0.0B5H.2 0.0B5H.1 0.0B5H.0 0.0B6H.3 0.0B6H.2 0.0B6H.1 0.0B6H.0 0.0B7H.3 0.0B7H.2 0.0B7H.1 0.0B7H.0 0.0B8H.1 0.0B8H.0 0.0B9H.1 0.0B9H.0 0.0BAH.0 0.0BBH.0 0.0BCH.0 0.0BDH.0 0.0BEH.3 0.0BEH.0 0.0BFH.3 0.0BFH.0 Description IDC background color specification enable flag Bit 2 of IDC background color specification flag Bit 1 of IDC background color specification flag Bit 0 of IDC background color specification flag IDC enable flag Bit 1 of PLL unlock flip-flop sensibility selection flag Bit 0 of PLL unlock flip-flop sensibility selection flag VRAM selection flag I pin selection flag Character dot (vertical) selection flag Selection flag for space between displayed characters P1B2 pin edge detection flag I/O selection flag of P1B3 pin I/O selection flag of P1B2 pin I/O selection flag of P1B1 pin I/O selection flag of P1B0 pin I/O selection flag of P0B3 pin I/O selection flag of P0B2 pin I/O selection flag of P0B1 pin I/O selection flag of P0B0 pin I/O selection flag of P0A3 pin I/O selection flag of P0A2 pin I/O selection flag of P0A1 pin I/O selection flag of P0A0 pin Bit 1 of SIO0 interrupt source register Bit 0 of SIO0 interrupt source register Bit 1 of SIO0 shift clock frequency selection flag Bit 0 of SIO0 shift clock frequency selection flag IDC VRAM pointer interrupt request flag Basic timer 2 interrupt request flag Timer 1 interrupt request flag Timer 0 interrupt request flag INT0 pin interrupt status flag INT0 pin interrupt request flag INTNC pin interrupt status flag INTNC pin interrupt request flag 330 PD17068 22.6 PERIPHERAL HARDWARE REGISTER Symbol IDCORG ADCR SIO0SFR HSC TM1M TM1C SIO1SFR PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5 PWMR6 PWMR7 PWMR8 WTMSEC WTMMIN WTMHR WTMDAY AR PLLR IDCVP IDCVPR TM0M TM0C Attribute DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT Value 01H 02H 03H 04H 05H 06H 07H 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1AH 1BH 1CH 1DH 40H 41H 42H 43H 46H 47H Read/ write R/W R/W R/W R R/W R R/W W W W W W W W W W R/W R/W R/W R/W R/W R/W R R/W R/W R Description IDC start position setting register A/D-converter reference-voltage (VREF) setting register SIO0 shift register HSYNC counter Timer 1 modulo register Timer 1 counter SIO1 shift register PWM data register 0 PWM data register 1 PWM data register 2 PWM data register 3 PWM data register 4 PWM data register 5 PWM data register 6 PWM data register 7 PWM data register 8 Register setting seconds of watch timer Register setting minutes of watch timer Register setting hours of watch timer Register setting days of watch timer Address register for GET/PUT/PUSH/CALL/BR/MOVT/MOVTH/MOVTL instructions PLL data register IDC VRAM pointer IDC VRAM pointer reference data register Timer 0 modulo register Timer 0 counter 22.7 OTHERS Symbol DBF IX Attribute DAT DAT Value 0FH 01H Description Fixed operand value for a PUT/GET/MOVT instruction Fixed operand value for an INC instruction 331 PD17068 23. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Ta = 25 C) Parameter Supply voltage Input voltage Output voltage Output high current Symbol VDD VI VO IOH Conditions Rated value -0.3 to +6.0 -0.3 to VDD + 0.3 Unit V V V mA mA mA mA mA mA V C C Except P1A, P2B, and P2C One pin All pins -0.3 to VDD + 0.3 -12 -20 12 20 17 60 13 -40 to +85 -55 to +125 Output low current IOL1 One pin (except P1A) All pins (except P1A) Output low current IOL2 One pin (P1A only) All pins (P1A only) Output withstand voltage Operating temperature Storage temperature VBDS Topt Tstg P1A, P2A, P2B, P2C Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values. RECOMMENDED OPERATION RANGE (Ta = -40 to +85 C) Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Data hold voltage Output withstand voltage Supply voltage rise time Input amplitude VDDR VBDS trise VIN When only the CPU is operating When only the watch timer is operating (CPU is stopped) When clock is stopped (Ta = 25 C) P1A, P2A, P2B, P2C VDD = 0 4.5 V VCO 0.7 Conditions Min. 4.5 3.5 2.2 2.2 Typ. 5.0 5.0 5.0 Max. 5.5 5.5 5.5 5.5 12.5 500 VDD Unit V V V V V ms VP-P 332 PD17068 DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 5 V 10 %) Parameter Supply current Symbol IDD1 Conditions When all functions are operating, VDD = 5 V, Ta = 25 C, fIN = 20 MHz, VIN = 0.7 VP-P, When IDC is operating, OSCIN = 10 MHz, When a sine signal is input to the XIN pin, (fIN = 8 MHz, VIN = VDD) When the CPU and PLL are operating, VDD = 5 V, Ta = 25 C, fIN = 20 MHz VIN = 0.7 VP-P, When a sine signal is input to the XIN pin, (fIN = 8 MHz, VIN = VDD) When only the CPU is operating, VDD = 5 V, Ta = 25 C, When a sine signal is input to the XIN pin, (fIN = 8 MHz, VIN = VDD) When the HALT instruction is executed, VDD = 5 V, Ta = 25 C, When a sine signal is input to the XIN pin, (fIN = 8 MHz, VIN = VDD) When the main clock is stopped and the watch timer is operating VDD = 5 V, Ta = 25 C When the main clock and watch timer are stopped VDD = 2.5 V, Ta = 25 C P0A, P0B, P1B, P1C, P2D CE, INT0, INTNC, VSYNC, HSYNC P0D P0A, P0B, P0D, P1B, P1C, P2D CE, INT0, INTNC, VSYNC, HSYNC P0A2, P0A3, P0B, P0C, P1B, P1C, BLANK, RED, GREEN, BLUE, P1D, P2D, EO VOH = VDD - 1 V P0A, P0B, P0C, P1B, P1C, BLANK, RED, GREEN, BLUE, P1D, P2A, P2B, P2C, P2D, EO, PWM VOL = 1 V P1A VCO P1A, P2A, P2B, P2C EO P0D (KEY) P0D (KEY) P0D (KEY) VOL = 1 V VIH = VDD VO = 12.5 V VO = VDD or 0 V VIH = VDD VIH = VDD = 5 V VIH = VDD = 5 V, Ta = 25 C Min. Typ. 20 Max. 23 Unit mA IDD2 9.0 12 mA IDD3 7.5 9 mA IDD4 2.5 3 mA Data hold current IDDR1 4 15 A IDDR2 Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 Output high current IOH 3 0.7VDD 0.8VDD 0.7VDD 15 A V V V 0.2VDD 0.2VDD -1 -5 V V mA Output low current IOL1 1 8.5 mA IOL2 Input high current Output leakage high current Output off leakage current Built-in pull-down resistor IIH ILOH IL RPD1 RPD2 RPD3 15 0.1 33 0.85 1.3 0.5 10-3 1 69 56 41 mA mA A A k k k 19 23 29 36 36 36 333 PD17068 AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 5 V 10 %) Parameter Input frequency 1 Symbol fVCO Conditions When a sine signal is input to the VCO pin VIN = 0.7VP-P TMIN (P1B3) HSCNT (P0B3) 50 % duty cycle Min. 0.7 Typ. Max. 20 Unit MHz Input frequency 2 Input frequency 3 fTMR fHS 45 10 65 20 Hz kHz A/D CONVERTER CHARACTERISTICS (Ta = -10 to +50 C, VDD = 5 V 10 %) Parameter A/D conversion absolute accuracy A/D conversion resolution A/D input impedance Symbol ADC0 to ADC7 Conditions Min. Typ. 1 Max. 1.5 6 Unit LSB ADC0 to ADC7 bit ADC0 to ADC7 1 M 334 PD17068 24. PACKAGE DRAWINGS 23.20.4 20.00.2 80 81 51 50 14.00.2 17.20.4 3.0 MAX. 0.8 100 1 31 30 0.6 0.300.10 0.15 M 0.65 1.60.2 2.7 0.12 0.80.2 0.15 +0.10 -0.05 0.10.1 S100GF-65-3BA-1 55 335 PD17068 25. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD17068. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 25-1 Soldering Conditions for Surface-Mount Devices PD17068GF-xxx-3BA: PD17068GF-Exx-3BA: Soldering process Infrared ray reflow 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (at 210 C or more) Maximum allowable number of reflow processes: 2 Exposure limit Note: 7 days (20 hours of pre-baking is required at 125 C afterward.) VPS VP15-207-2 Wave soldering WS60-207-1 Partial heating method - Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: Temperature of 25 C and maximum relative humidity at 65% or less Caution Do not apply more than a single process at once, except for "Partial heating method." 336 PD17068 APPENDIX A. NOTES ON CONNECTING A CRYSTAL When connecting the crystal, run wires in the portion surrounded by dotted lines in Fig. A-1 according to the following rules to avoid effects such as stray capacitance: * Minimize the wiring. * Never cause the wires to cross other signal lines or run near a line carrying a large varying current. * Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as ground. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator. Note the following (1) to (3) when capacitors are connected or the oscillation frequency is adjusted. (1) When C1 and C2 are too large, the oscillation activation characteristics deteriorate and the supply current increases. (2) The trimmer capacitor for adjusting the oscillation frequency is usually connected to the XIN (or XTIN) pin. However, this connection may cause deterioration of oscillation stability, depending on the crystal used. (In this case, connect the trimmer capacitor to the XOUT (or XTOUT) pin.) To evaluate the oscillation, use the crystal to be actually used. (3) Adjust the oscillation frequency while measuring the VCO oscillation frequency. If the probe is connected to pin XOUT, XTOUT, XIN, or XTIN, the oscillation frequency cannot be correctly adjusted because of the probe capacitance. Fig. A-1 Crystal Connection PD17068 XOUT, XTOUT XIN, XTIN 8 MHz crystal C2 C1 337 PD17068 APPENDIX B. DEVELOPMENT TOOLS The following support tools are available for developing programs for the PD17068. Hardware Name In-circuit emulator IE-17K IE-17K-ETNote 1 EMU-17KNote 2 Description The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series. The IE-17K and IE-17K-ET are connected to the PC-9800 series (host machine) or IBM PC/ATTM through the RS-232-C interface. The EMU-17K is inserted into the extension slot of the PC-9800 series (host machine). Use the system evaluation board (SE board) corresponding to each product together with one of these in-circuit emulators. SIMPLEHOSTTM, a man machine interface, implements an advanced debug environment. The EMU-17K also enables user to check the contents of the data memory in real time. The SE-17008 is an SE board for the PD17068, PD17P068, and PD17008. It is used solely for evaluating the system. It is also used for debugging in combination with the in-circuit emulator. The EP-17068GF is an emulation probe for the PD17068 and PD17P068. The EV-9200GF-100 is a conversion socket for the 100-pin plastic QFP (14 x 20 mm). It is used to connect the EP-17068GF to the target system. The AF-9703, AF-9704, AF-9705, and AF-9706 are PROM writers for the PD17P068. Use one of these PROM writers with the program adapter, AF-9808L, to program the PD17P068. SE board (SE-17008) Emulation probe (EP-17068GF) Conversion socket (EV-9200GF-100Note 3) PROM Programmer AF-9703Note 4 AF-9704Note 4 AF-9705Note 4 AF-9706Note 4 Programmer adapter (AF-9808LNote 4) The AF-9808L is a socket unit for the PD17P068. It is used with the AF-9703, AF-9704, AF-9705, or AF-9706. Notes 1. Low-end model, operating on an external power supply 2. The EMU-17K is a product of IC Co., Ltd. Contact IC Co., Ltd. (Tokyo, 03-3447-3793) for details. 3. The EP-17068GF is supplied together with one EV-9200GF-100. A set of five EV-9200GF-100s is also available. 4. The AF-9703, AF-9704, AF-9705, AF-9706, and AF-9808L are products of Ando Electric Co., Ltd. Contact Ando Electric Co., Ltd. (Tokyo, 03-3733-1151) for details. 338 PD17068 Software Host machine PC-9800 series Distribution media 5.25-inch, 2HD 3.5-inch, 2HD IBM PC/AT 5.25-inch, 2HC 3.5-inch, 2HC 5.25-inch, 2HD MS-DOS 3.5-inch, 2HD 5.25-inch, 2HC 3.5-inch, 2HC Support software (SIMPLEHOST) SIMPLEHOST, running on the PC-9800 MS-DOS series WindowsTM , provides manmachine-interface in developing programs by using a personal computer and the IBM PC DOS in-circuit emulator. PC/AT Windows 5.25-inch, 2HD 3.5-inch, 2HD 5.25-inch, 2HC 3.5-inch, 2HC Name 17K series assembler (AS17K) Description AS17K is an assembler applicable to the 17K series. In developing PD17068 programs, AS17K is used in combination with a device file (AS17068). OS Part number S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K S5A10AS17068 S5A13AS17068 S7B10AS17068 S7B13AS17068 S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K MS-DOS TM PC DOS TM Device file (AS17068) AS17068 is a device file for the PD17068 and PD17P068 . It is used together with the assembler (AS17K), which is applicable to the 17K series. PC-9800 series IBM PC/AT PC DOS Remark The following table lists the versions of the operating systems described in the above table. OS MS-DOS PC DOS Windows Versions Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1 Note MS-DOS versions 5.00 and 5.00A and PC DOS Ver. 5.0 are provided with a task swap function. This function, however, cannot be used in these software packages. 339 PD17068 Cautions on CMOS Devices # Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. $ CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. % Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2 C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. PD17068 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. |
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